Cleaning up the Mess - ISPASS'26 Talk by Nisa Bostanci and Haocong Luo
The ISPASS 2026 presentation by Nisa Bostanci and Haocong Luo challenges a recent best‑paper that claimed the open‑source DRAM simulator Emulator 2 dramatically under‑performed real hardware. The speakers identified three fatal flaws: missing source code prevented replication; the simulation used only eight DDR5 channels while the real system had sixteen, halving bandwidth; and cache latency was set to zero with excessive status registers, yielding unrealistically low latency. Similar statistical misuse was found in the DO framework. After rebuilding the artifacts and correcting the configuration, their experiments showed Emulator 2 achieving bandwidth within 2 % of the theoretical maximum and latency rising proportionally with load—behaviour matching the physical platform. The authors also released the corrected code, data, and a new Emulator 2.1 branch, and highlighted specific graph comparisons. The work underscores the need for transparent, reproducible simulation practices. By publishing four concrete best‑practice guidelines, the team aims to prevent misleading results that can steer memory‑system research off course and erode confidence in simulation‑driven design.
Digital Design & Comp. Arch: L22: Memory Hierarchy and Caches (Spring 2026)
Lecture 22 of the Digital Design & Computer Architecture course examines the memory hierarchy and cache architectures, reviewing how different memory technologies—SRAM, DRAM, and emerging non‑volatile options—fit into a multi‑level system. The instructor stresses that each level trades speed, capacity, cost,...
Digital Design & Computer Architecture D10: Problem-Solving Session 10 (Spring 2026)
The session opened with a dual focus on VLIW (referred to as VIW) architectures and systolic‑array designs, providing a quick theoretical refresher before diving into hands‑on exercises. The instructor emphasized that VLIW’s performance hinges on the compiler’s ability to group...
Digital Design & Comp. Arch: L20b: GPU Programming (Spring 2026)
The lecture introduces GPU programming as a cornerstone of modern high‑performance computing, shifting focus from traditional graphics rendering to general‑purpose acceleration. It outlines the CUDA and OpenCL ecosystems, emphasizing the bulk‑synchronous parallel model that structures code into thread blocks, warps,...
Digital Design & Comp. Arch: L20: GPU Architectures (Spring 2026)
The lecture focuses on modern GPU architectures, positioning them as flexible extensions of classic SIMD, array, and vector processors. Building on last week’s SIMD fundamentals, the professor explains how GPUs blend space‑time parallelism, allowing scalar instructions to be dispatched across...
Digital Design & Computer Architecture D9: Problem-Solving Session 9 (Spring 2026)
The video walks through a problem‑solving session on branch prediction, a core technique for handling control dependencies in modern pipelined CPUs. After a brief recap of terminology such as control dependency and branch‑resolution penalty, the instructor introduces several classic prediction...
Seminar in Comp. Arch. - S3: Conduit (Spring 2026)
The seminar introduced Conduit, a programmer‑transparent near‑data processing (NDP) framework that leverages the heterogeneous compute resources inside modern SSDs—embedded cores, DRAM, and flash chips. By abstracting offloading decisions away from developers, Conduit aims to overcome the adoption barriers of prior...
Digital Design & Comp. Arch: L19: SIMD Architectures (Spring 2026)
The lecture introduces single‑instruction‑multiple‑data (SIMD) architectures, emphasizing their central role in today’s high‑performance computing, especially for machine‑learning workloads such as GPUs. It reviews data‑level parallelism, explains Flynn’s taxonomy, and distinguishes array processors (space‑parallel) from vector processors (time‑parallel). The discussion highlights vector...
P&S Arch. & Algo. For Health & Life Sciences - L6: Overview of Genomic Workflows (II) (Spr 2026)
The sixth lecture of the P&S Architecture & Algorithms for Health & Life Sciences series dives into genomic workflow analysis, concentrating on the read‑mapping stage that stitches sequenced fragments into a complete genome. It revisits earlier concepts—why genomics matters, base‑calling,...
Scaling the Memory Wall: Towards 3D-DRAM-Based Accelerators for Efficient Generative Inference
The talk addresses the growing "memory wall" that hampers generative AI inference and proposes 3D‑DRAM‑based accelerators as a hardware remedy. While processor speed has risen 50‑60% annually, memory bandwidth lags at 7‑8%, turning the decode stage of large language models...
Digital Design & Computer Architecture D8: Problem-Solving Session 8 (Spring 2026)
The session focused on out‑of‑order execution and Thomas’s algorithm, reviewing how modern pipelines mitigate data dependencies through register renaming and dynamic scheduling. The instructor recapped lecture concepts before tackling a common exam problem that requires reverse‑engineering the Thomas algorithm from...
P&S Arch. & Algo. For Health & Life Sciences - L5: Overview of Genomic Workflows (I) (Spr 2026)
The lecture provides a holistic overview of genomic workflows, emphasizing why genomics is central to modern biology, medicine, and environmental monitoring. It revisits storage‑centric acceleration discussed earlier and expands to the full pipeline—from sample acquisition and sequencing to variant calling,...
Digital Design & Comp. Arch: L17: Branch Prediction (Spring 2026)
ETH Zurich’s Digital Design & Computer Architecture course released Lecture 17 on branch prediction, delivered by Prof. Onur Mutlu on April 23, 2026. The session explores static and dynamic prediction schemes, their impact on processor pipelines, and ties to emerging...
Seminar in Comp. Arch. - S1: ColumnDisturb & ABACuS (Spring 2026)
The seminar introduced column disturbance, a newly documented read‑disturbance effect in modern DRAM. Presenter Yong Jo explained the open‑bitline architecture of DDR4 and HBM2 chips, then described how aggressive activation of a single row can perturb bit‑lines across an entire...
"Can We Do Better?" Prof. Onur Mutlu's MICRO 2025 Keynote Talk at Seoul - 21.10.2025
Prof. Onur Mutlu’s MICRO 2025 keynote, titled “Can We Do Better?”, framed the memory bottleneck as the central obstacle to energy‑efficient, high‑performance computing. He argued that while the industry has long treated computing as an energy problem, the majority of...