Onur Mutlu Lectures

Seminar in Comp. Arch. - S1: ColumnDisturb & ABACuS (Spring 2026)

The seminar introduced column disturbance, a newly documented read‑disturbance effect in modern DRAM. Presenter Yong Jo explained the open‑bitline architecture of DDR4 and HBM2 chips, then described how aggressive activation of a single row can perturb bit‑lines across an entire subarray and even neighboring subarrays, causing bit flips far beyond the localized impact of classic row‑hammer or row‑press attacks. Experimental results showed the phenomenon is ubiquitous: all 216 DDR4 and four HBM2 chips tested exhibited column‑disturbance flips, and the time to first error shrank dramatically in newer die revisions—up to five‑fold faster in some 8 GB SK Hynix parts. In the worst case, a flip occurred in 63.6 ms, well within DDR4’s 64 ms refresh interval, meaning the error can happen before the next mandatory refresh. The data also revealed that column disturbance generates far more bit flips than row‑hammer, row‑press, or ordinary retention failures—up to 35× higher in certain Samsung devices. Flips were concentrated in the aggressor subarray’s shared bit‑lines, with neighboring subarrays experiencing roughly half the rate due to the open‑bitline sharing. Moreover, the direction of flips (1→0 versus 0→1) differed from other disturbances, underscoring a distinct physical mechanism. These findings imply that existing DRAM reliability models and mitigation techniques (e.g., targeted refresh or row‑hammer detection) are insufficient. Designers may need to revisit open‑bitline layouts, introduce more aggressive refresh schedules, or develop hardware‑level monitoring to detect column‑wide activity. For data‑center operators and system architects, the risk of silent data corruption grows as process nodes shrink, making proactive countermeasures essential.