An Agent Autonomously Builds a 1.5 GHz Linux-Capable RISC-V CPU

Key Takeaways

• DC produced 1.5 GHz RISC‑V core in 12 hours.
• Design meets RV32I, ZMMUL, 5‑stage pipeline specs.
• Achieves CPI ≤ 1.5, targeting CoreMark performance.
• Uses OpenROAD, ASAP7 PDK for GDSII output.
• Precise specs critical for AI‑generated hardware quality.

Summary

Verkor’s AI agent, Design Conductor (DC), autonomously generated a 1.5 GHz Linux‑capable RISC‑V CPU in roughly 12 hours. The chip, named VerCore, implements RV32I and ZMMUL extensions, a five‑stage in‑order pipeline, and meets a CPI of ≤ 1.5 while targeting CoreMark scores. DC produced both RTL and a physical GDSII layout using the OpenROAD flow on the ASAP7 PDK. The demonstration shows that an AI system can deliver a silicon‑ready design with minimal human intervention.

Pulse Analysis

Artificial intelligence is rapidly moving beyond software code generation into the realm of silicon design. Verkor’s Design Conductor (DC) illustrates this shift by taking a tightly written specification and, within half a day, delivering a complete RISC‑V processor that can boot Linux. The system leverages the OpenROAD open‑source physical design flow and the ASAP7 predictive process, producing RTL, synthesis reports, and a GDSII file ready for tape‑out. By meeting a CPI of 1.5 and targeting a 1.6 GHz clock, the AI‑crafted core demonstrates performance levels previously reserved for seasoned hardware teams.

The technical breakthrough hinges on two factors: exhaustive, measurable specifications and the integration of modern EDA tools. DC required explicit performance constraints—such as cycle‑per‑instruction targets and signal timing windows—to guide its synthesis decisions. It then orchestrated the entire flow, from register‑file flip‑flop implementation to cache interface generation, and finally ran Spike simulations to validate functional correctness. This level of end‑to‑end automation reduces the reliance on manual RTL debugging and iterative tape‑out cycles, cutting development costs and accelerating innovation for startups and established fabless players alike.

Industry observers see parallels with recent AI advances in software compilation, like Anthropic’s Claude C compiler, which can produce bootable binaries with limited oversight. The convergence of AI in both software and hardware stacks suggests a future where design engineers focus on high‑level architecture and constraint definition, while AI handles the granular implementation. As AI‑driven design tools mature, they could democratize chip creation, enable rapid prototyping, and reshape competitive dynamics across the semiconductor ecosystem.