Arteris Highlights a Path to Scalable Multi-Die Systems at the Chiplet Summit

Key Takeaways

• Chiplet designs overcome monolithic die size limits
• Ncore provides coherent communication across up to four chiplets
• Open standards like UCIe drive ecosystem interoperability
• Sub‑assembly flexibility supports product‑line diversification

Summary

At the Chiplet Summit, Arteris highlighted its multi‑die interconnect portfolio, showcasing FlexGen, FlexNoC and the coherent Ncore platform for AI, HPC and automotive ADAS applications. The solutions support up to four die‑to‑die links per chiplet and flexible sub‑assembly configurations, enabling heterogeneous designs that surpass monolithic die limits. Ashley Stevens emphasized the industry’s shift toward chiplet‑based architectures and the importance of open standards such as UCIe and AMBA CXS. Arteris positioned its technology as a bridge to larger, higher‑yield, cost‑effective systems.

Pulse Analysis

The semiconductor landscape is rapidly moving away from traditional monolithic silicon as Moore’s Law slows and AI workloads double roughly every six months. Designers are turning to chiplet‑based architectures to break reticle size constraints, improve yields, and reuse proven IP blocks across product families. This shift enables heterogeneous integration of CPUs, GPUs, AI accelerators and memory on a single package, delivering the performance density required for next‑generation data‑center and automotive ADAS solutions.

Arteris leverages its long‑standing NoC expertise to address the interconnect challenge inherent in multi‑die systems. Its FlexGen and FlexNoC IPs handle non‑coherent traffic using standard protocols like AMBA AXI, while the Ncore coherent fabric extends AMBA CXS across up to four chiplets, offering low‑latency, cache‑coherent communication. Features such as port remapping and sub‑assembly support let manufacturers reconfigure die counts without redesign, reducing time‑to‑market and enabling differentiated product lines from a common silicon base.

Despite technical progress, widespread chiplet adoption hinges on ecosystem alignment. Open standards such as UCIe, PCIe and AMBA CXS are essential for cross‑vendor interoperability, verification, and address mapping. Collaboration among IP vendors, EDA tools, foundries and standards bodies will streamline integration and lower verification risk. As these standards mature, Arteris’s scalable interconnects are poised to become a foundational layer for the AI‑driven, heterogeneous compute platforms that will dominate the market in the coming decade.