Axiomise Introduces nocProve to Transform NoC Design Verification

Key Takeaways

• nocProve is first configurable formal verification tool for NoCs.
• Handles multiple clock domains, virtual channels, routing policies.
• Reduces verification time to hours for complex designs.
• Detects deadlocks, livelocks missed by simulation.
• Cuts silicon respins, lowers AI chip development risk.

Summary

Axiomise has launched nocProve, the first configurable formal verification application dedicated to Network-on-Chip (NoC) designs. The tool leverages the company’s proprietary proof engine to exhaustively prove correctness across multiple clock domains, virtual channels, and routing schemes. By automating proof generation from Verilog/VHDL and SystemVerilog Assertions, nocProve can validate complex open‑source NoCs within hours, cutting manual effort. Early detection of deadlocks and other rare faults promises to reduce costly silicon respins for AI accelerators and high‑performance chips.

Pulse Analysis

Network‑on‑Chip architectures are the communication backbone of modern processors, but their growing complexity—multiple clock domains, virtual channels, and custom routing—makes verification a formidable challenge. Traditional simulation can only explore a finite set of scenarios, leaving rare corner‑case bugs like deadlocks undetected. Formal verification offers mathematical certainty, yet its state‑space explosion has historically limited its use for NoCs. The industry therefore faces a trade‑off between thoroughness and practicality, especially as AI accelerators demand ever‑more bespoke interconnects.

nocProve addresses this gap by embedding a configurable formal engine into Axiomise’s verification platform. Engineers feed Verilog or VHDL designs along with SystemVerilog Assertions, and the tool automatically synthesizes exhaustive proofs tailored to the specific bus protocols, channel types, and routing policies in use. In benchmark runs, nocProve validated complex open‑source NoC designs with high throughput and multiple simultaneous transactions within a few hours—far faster than conventional formal tools. This automation reduces manual effort, shortens verification schedules, and enables early detection of subtle bugs that would otherwise surface late in silicon.

The broader impact of nocProve extends to high‑stakes markets such as AI accelerators, data‑center processors, and high‑performance computing chips, where a single interconnect flaw can delay product launches and inflate costs. By delivering exhaustive confidence without prohibitive compute demands, the tool helps chipmakers lower the risk of expensive respins and accelerate innovation cycles. As semiconductor designs continue to diversify and performance targets rise, formal NoC verification tools like nocProve are poised to become essential components of the standard chip development flow.