M31 Validates MIPI M-PHY v5.0 IP on 4nm, Advances 3nm Development to Enable UFS 4.1 Applications

Key Takeaways

• MIPI M‑PHY v5.0 validated on 4 nm process
• 23.32 Gb/s per lane in HS‑G5 mode
• Integrated UFSHCI v4.1 controller simplifies SoC design
• ISO 26262 safety certification meets automotive requirements
• Development progressing toward 3 nm node

Summary

M31 Technology announced that its silicon‑proven MIPI M‑PHY v5.0 IP has been validated on a 4 nm process and is now being advanced toward 3 nm. The PHY delivers up to 23.32 Gb/s per lane in HS‑G5 mode, doubling the speed of the prior generation. M31 bundles the PHY with a JEDEC‑compliant UFSHCI v4.1 controller and UniPro IP, creating a one‑stop UFS 4.1 solution. The offering includes ISO 26262 functional‑safety certification, targeting smartphones, automotive cockpits, and AI edge devices.

Pulse Analysis

The storage interface market is at a tipping point as AI inference and autonomous‑driving systems demand ever‑higher data rates. UFS 4.1, the latest iteration of the Universal Flash Storage standard, promises multi‑gigabit per second throughput, but its success hinges on a robust physical layer. M31’s validation of MIPI M‑PHY v5.0 on a 4 nm node demonstrates that the industry can meet these performance targets, delivering 23.32 Gb/s per lane—twice the speed of the previous HS‑G4 generation—while maintaining signal integrity through adaptive equalization and multi‑amplitude signaling.

Beyond raw speed, power efficiency and safety are critical for mobile and automotive applications. M31’s PHY incorporates an optimized hibernate mode that extends battery life without sacrificing performance, and the integrated solution adheres to ISO 26262 functional‑safety standards, a prerequisite for automotive cockpits and safety‑critical systems. By packaging the PHY with a JEDEC‑compliant UFSHCI v4.1 controller and UniPro control‑layer IP, M31 reduces design complexity, allowing semiconductor vendors to accelerate SoC development cycles and focus on differentiating features rather than low‑level integration.

Looking ahead, the move toward a 3 nm implementation positions M31 to stay ahead of the semiconductor roadmap, offering customers a path to even higher bandwidth and lower power consumption as process nodes shrink. This advancement strengthens M31’s competitive stance against larger IP vendors and aligns with the broader ecosystem’s push for edge AI, 5G‑enabled devices, and next‑generation automotive platforms. Companies that adopt M31’s UFS 4.1 solution can expect faster time‑to‑market, reduced engineering risk, and a scalable foundation for future high‑performance storage demands.