AMD Says Intel's SMT Cut Could Accelerate EPYC Server Share Gain

Why It Matters

The threading decision directly impacts total cost of ownership for data‑center operators. Software licensing that scales with thread count can add millions of dollars to annual spend, making SMT‑enabled CPUs like EPYC more financially attractive. Additionally, the ability to pack more threads per socket reduces the number of physical sockets required, lowering power, cooling, and rack‑space demands—critical factors as hyperscale facilities push toward higher density. If AMD can translate its architectural advantage into measurable market share gains, the competitive balance in the x86 server market could shift, encouraging more diverse supplier ecosystems and potentially accelerating innovation in both performance and efficiency. Intel’s response—re‑introducing SMT in Granite Rapids—will test whether the temporary sacrifice of threading was a strategic misstep or a calculated trade‑off for short‑term gains in other areas.

Key Takeaways

• AMD VP Madhu Rangarajan says Intel's removal of HyperThreading in Diamond Rapids will boost EPYC market share.
• Intel's Diamond Rapids will launch later 2026 on 18A node without SMT, while AMD's Venice will retain SMT with up to 256 cores/512 threads.
• Srini Krishna counters that Intel's value proposition lies in security, efficiency, and platform experience.
• SMT absence may increase software licensing costs for data‑center workloads that charge per thread.
• Intel plans to re‑introduce SMT with Granite Rapids in 2027, aiming to close performance gaps.

Pulse Analysis

Intel’s decision to drop SMT in its Diamond Rapids line appears to be a calculated gamble: by simplifying core design and leveraging the 18A process, the company hopes to extract higher clock speeds and better power efficiency. Historically, Intel has used SMT to compensate for lower per‑core performance relative to AMD, especially in multi‑threaded server workloads. The current move flips that script, betting that security features, integrated accelerators, and a tighter platform stack will outweigh the loss of parallelism.

AMD, meanwhile, is doubling down on the traditional EPYC playbook—massive core counts, full SMT, and a focus on licensing economics. Venice’s 256‑core, 512‑thread configuration could be a game‑changer for cloud providers that run heavily threaded applications, from databases to AI inference. The real test will be how quickly AMD can bring Venice to market and whether its performance per watt can match Intel’s claims. If Venice delivers, we could see a measurable shift in server‑CPU market share, potentially eroding Intel’s roughly 70% dominance in the data‑center segment.

Looking ahead, the competitive dynamics will hinge on timing. Intel’s Granite Rapids, slated for 2027, promises to bring SMT back, suggesting the company views the current omission as a short‑term tactical move rather than a permanent architectural shift. If Intel can re‑introduce SMT without sacrificing the security and efficiency gains it touts, it may neutralize AMD’s advantage. Conversely, a delayed or under‑performing Granite Rapids could cement EPYC’s gains, prompting a longer‑term rebalancing of the server CPU market. Stakeholders should watch the upcoming product demos, benchmark releases, and early‑adopter feedback closely, as they will set the tone for data‑center procurement strategies through the next hardware cycle.