­EnSilica Joins UK CHERI Adoption Collective to Accelerate Secure-by-Design Silicon

Why It Matters

By integrating CHERI’s capability hardware, EnSilica helps close the memory‑safety gap that fuels 70% of software vulnerabilities, strengthening the resilience of essential UK services. This collaboration accelerates the adoption of secure‑by‑design silicon across sectors, offering a competitive edge in a market increasingly focused on cyber‑risk mitigation.

Key Takeaways

• EnSilica joins CHERI Adoption Collective with UK infrastructure leaders.
• CHERI adds hardware memory safety, reducing 70% software bugs.
• EnSura™ platform integrates CHERI and post‑quantum cryptography.
• Collective targets secure, low‑cost legacy and next‑gen systems.
• Participation boosts UK semiconductor security ecosystem.

Pulse Analysis

Memory‑safety flaws remain the leading cause of cyber‑incidents, accounting for roughly 70 percent of software vulnerabilities. The Capability Hardware Enhanced RISC Instructions (CHERI) architecture tackles this problem at the silicon level by attaching fine‑grained capabilities to pointers, effectively preventing out‑of‑bounds reads and writes. Recognising the strategic importance of such protection, the UK Department for Science, Innovation & Technology, together with PA Consulting, launched the CHERI Adoption Collective to pool expertise from energy, defence, telecom and semiconductor players. The initiative seeks to create a scalable, cost‑effective pathway for retrofitting both legacy equipment and future designs with built‑in memory safety.

EnSilica’s entry into the collective leverages its EnSura™ microcontroller, the first commercial CHERI‑enabled RISC‑V solution that also incorporates post‑quantum cryptography primitives. By embedding capability hardware directly into the core, EnSura delivers deterministic security guarantees without sacrificing functional safety certifications required in automotive and industrial control environments. The platform’s modular architecture allows system integrators to adopt hardware‑enforced protection with minimal software rewrites, accelerating time‑to‑market for secure products. This combination of CHERI and quantum‑resistant algorithms positions EnSilica as a differentiated supplier in a market where regulators increasingly demand provable security assurances.

The collective’s broader impact extends beyond individual chip designs, fostering a UK‑wide ecosystem that aligns supply‑chain resilience with national cyber‑defence objectives. Participation by major operators such as BT, National Grid and SSE signals a commitment to hardening critical infrastructure against sophisticated attacks. As more OEMs adopt CHERI‑based silicon, economies of scale are expected to drive down costs, making secure‑by‑design hardware accessible to midsize manufacturers. For investors and industry watchers, the collaboration marks a pivotal shift toward hardware‑first security strategies, a trend likely to shape semiconductor roadmaps globally over the next decade.