Precision In Depth: Extraction Workflows For CFETs And Buried Power Rails

Why It Matters

Accurate 3‑D extraction is essential to avoid IR‑drop and signal‑integrity failures in next‑generation nodes, directly impacting time‑to‑market and product yield.

Key Takeaways

• CFETs stack n- and p-type transistors vertically.
• Buried power rails route supply beneath active layers.
• Extraction must model front and back metal, TSVs, non‑Manhattan.
• Siemens Calibre xACT provides unified 3‑D parasitic extraction.
• Accurate extraction prevents IR‑drop, signal integrity failures.

Pulse Analysis

The semiconductor industry faces a hard wall at sub‑5 nm nodes, where planar scaling no longer yields performance gains. Engineers are therefore embracing vertical integration: CFETs place complementary transistors on top of each other, while buried power rails act like underground highways for supply voltage. This approach not only doubles transistor density without expanding the chip footprint, but also liberates upper metal layers for high‑speed interconnects, a critical advantage as data‑center and mobile workloads demand ever‑greater bandwidth.

Yet the benefits come with a hidden cost. The multi‑layered stack creates parasitic resistances, capacitances, and even inductances that span front‑side, back‑side, and through‑silicon vias. Traditional RC extraction scripts, designed for two‑dimensional layouts, miss these cross‑layer couplings, leading to inaccurate IR‑drop analysis and timing errors. Designers must therefore adopt physics‑aware solvers capable of handling non‑Manhattan routing, heterogeneous dielectrics, and the intricate geometry of TSVs and BPRs. Without such precision, silicon prototypes risk late‑stage failures that can cost millions.

Siemens addresses this gap with Calibre xACT, a single‑environment extraction platform that ingests full‑stack geometry and applies custom rule decks for CFET and BPR processes. The workflow begins with comprehensive layout import, followed by validation of material properties and sheet resistances supplied by the foundry. Iterative extraction then generates detailed parasitic netlists that feed directly into static timing, signal‑integrity, and power‑analysis tools. By unifying front‑ and back‑side extraction, Calibre xACT reduces respin cycles, shortens design closure, and gives manufacturers the confidence to push silicon roadmaps into the 3 nm and beyond era.