Hardware

MCCSys-5: 5th Workshop on Memory-Centric Computing Systems, Held with ASPLOS 2026 - 23 March 2026

Onur Mutlu Lectures
Onur Mutlu Lectures•Mar 23, 2026

Why It Matters

Addressing the memory bottleneck is essential for scaling AI and data‑intensive applications while curbing energy costs, making memory‑centric designs a strategic priority for the computing industry.

Key Takeaways

  • •Memory bottleneck dominates performance, energy, and cost in modern systems.
  • •Processing-in-memory (PIM) can reduce data movement overhead dramatically.
  • •Current architectures waste >90% energy on memory traffic for AI workloads.
  • •Workshop highlights research on autonomous memory management and security attacks.
  • •Upcoming MCCSys-7 will accept papers for inclusion in ASPLOS proceedings.

Summary

The fifth Memory‑Centric Computing Systems (MCCSys‑5) workshop, co‑located with ASPLOS 2026, gathered researchers to confront the growing memory bottleneck that now dominates performance, energy consumption, and hardware cost across data‑intensive workloads. Organizers outlined the agenda—keynotes on memory‑centric architectures, recent advances in processing‑in‑memory (PIM) using DRAM chips, and sessions on side‑channel and fault‑injection attacks—while inviting submissions for the upcoming MCCSys‑7 proceedings.

Presentations underscored that moving data between storage, memory, caches, and registers now accounts for the majority of system energy and latency. Empirical studies cited from Google’s data‑center and mobile workloads revealed that 60‑90% of total energy is spent on memory traffic, a figure that spikes to over 90% for edge neural networks and is expected to worsen with large language models. The disparity between a memory access (hundreds to thousands of times more energy‑intensive) and a simple compute operation was highlighted, illustrating why traditional processor‑centric designs are increasingly unsustainable.

Speakers used vivid analogies—a “10‑year‑old kid” test—to illustrate that despite dedicating 90‑95% of hardware real estate to data movement, memory remains the system’s choke point. Professor Phil Gibbons and others presented concrete PIM prototypes that autonomously manage memory, reducing data movement and mitigating security vulnerabilities such as side‑channel attacks. The workshop also featured a candid discussion on venue accessibility, emphasizing the need to lower barriers for under‑21 participants.

The implications are clear: future high‑performance and energy‑efficient computing will require a paradigm shift toward memory‑centric designs, distributed computation across memory and other near‑data components, and robust security models. Researchers are urged to contribute novel PIM architectures and security analyses to the forthcoming MCCSys‑7, which will publish accepted work in the ASPLOS proceedings, shaping the next generation of data‑centric systems.

Original Description

ASPLOS 2026: 5th Workshop on Memory-Centric Computing Systems (MCCSys)
Organizers: Ismail E. Yuksel, F. Nisa Bostanci, Ataberk Olgun, Dr. Zhiheng Yue, Dr. Mohammad Sadrosadati, Dr. Geraldo F. Oliveira, Professor Onur Mutlu
Workshop Overview:
This combined tutorial and workshop will focus on the latest advances in PIM technology, spanning both hardware and software. It will include novel PIM ideas, different tools and frameworks for conducting PIM research, and programming techniques and optimization strategies for PIM kernels. First, we will provide a series of lectures and invited talks that will provide an introduction to PIM, including an overview and a rigorous analysis of existing PIM hardware from industry and academia. Second, we will invite the broad PIM research community to submit and present their ongoing work on memory-centric systems. The program committee will favor papers that bring new insights on memory-centric systems or novel PIM-friendly applications, address key system integration challenges in academic or industry PIM architectures, or put forward controversial points of view on the memory-centric execution paradigm. We also consider position papers, especially from industry, that outline design and process challenges affecting PIM systems, new PIM architectures, or system solutions for real state-of-the-art PIM devices.
Recommended Readings:
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A Modern Primer on Processing in Memory
Processing Data Where It Makes Sense: Enabling In-Memory Computation
Processing-in-Memory: A Workload-Driven Perspective
Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture
Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-in-Memory Hardware
SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
Intelligent Architectures for Intelligent Computing Systems
RowHammer: A Retrospective
RECOMMENDED LECTURE VIDEOS & PLAYLISTS:
========================================
P&S Data-Centric Architectures: Fundamentally Improving Performance and Energy (Fall 2022)
P&S Programming Heterogeneous Computing Systems with GPUs and other Accelerators (Fall 2022)
Computer Architecture Fall 2022 Lectures Playlist:
Digital Design and Computer Architecture Spring 2022 Livestream Lectures Playlist:
Featured Lectures:
Interview with Professor Onur Mutlu:
The Story of RowHammer Lecture:
Accelerating Genome Analysis Lecture:
Memory-Centric Computing Systems Tutorial at IEDM 2021:
Intelligent Architectures for Intelligent Machines Lecture:

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