Seminar in Comp. Arch. - L3: Memory-Centric Computing II (Spring 2026)
Why It Matters
Processing‑in‑memory transforms the memory bottleneck into a performance lever, enabling faster, energy‑efficient data‑centric workloads that are critical for AI, analytics, and cloud services.
Key Takeaways
- •DRAM row‑clone enables 10× latency reduction for bulk copies.
- •In‑DRAM majority logic supports AND, OR, and NOT operations.
- •PIM‑enabled instructions allow seamless integration of memory compute.
- •SIMD‑UAM framework maps high‑level algorithms to DRAM primitives.
- •MIM‑DRAM improves granularity, expanding practical processing‑in‑memory workloads significantly.
Summary
The seminar continued the series on memory‑centric computing, shifting focus from near‑memory acceleration to true processing‑using‑memory (PUM). The lecturer reviewed prior work on 3‑D integration and specialized accelerators for graph processing and machine‑learning inference, then introduced the core PUM concepts that exploit DRAM’s analog behavior for computation.
Key technical insights included the row‑clone primitive, which copies an entire DRAM row with two consecutive activates, delivering more than 10× latency and 70× energy reductions when source and destination reside in the same subarray. By concurrently activating three rows, DRAM can compute a bitwise majority function, enabling AND, OR, and NOT operations directly in memory. These low‑cost analog operations address the data‑movement bottleneck highlighted by Google’s finding that copy‑related calls consume ~5% of data‑center cycles.
The lecture highlighted the SIMD‑UAM framework that translates high‑level algorithms into sequences of DRAM primitives (row‑clone, triple‑row activation, etc.) and introduces PIM‑enabled instructions that the memory controller executes transparently. Applications such as bitmap‑index databases, web‑search engines, and certain encryption tasks can achieve substantial speedups, while the newer MIM‑DRAM architecture refines execution granularity, making PUM viable for a broader range of workloads.
Implications are significant: hardware designers can embed compute capability into commodity DRAM without major redesign, software stacks must evolve to expose PIM instructions, and data‑intensive enterprises stand to reduce latency and energy costs dramatically. Continued research into granularity, programmability, and compiler support will determine how quickly these techniques move from labs to production systems.
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