Track Crossing on PCBs - Myth vs Reality
Why It Matters
Unrecognized crosstalk from orthogonal routing can degrade high‑speed signals, leading to data errors and costly redesigns.
Key Takeaways
- •Orthogonal routing on adjacent layers can cause significant crosstalk at high frequencies
- •Standard SI tools often miss this coupling; full EM analysis required
- •Crosstalk rises from -52 dB at 1 GHz to around -25 dB at 30 GHz
- •Phase relationship between signals dramatically affects coupling magnitude and pattern
- •Dense multi‑track buses may unintentionally form directional couplers, degrading signal integrity
Summary
The video tackles a common PCB myth: that routing one signal layer horizontally while the adjacent layer carries vertical traces is inherently safe from interference. The presenters demonstrate that, despite intuition and many signal‑integrity (SI) tools suggesting otherwise, electromagnetic (EM) coupling can be substantial, especially as frequencies climb.
Using full‑wave EM simulations on a typical stack‑up (100 µm dielectric, two 200 µm signal layers, and ground planes), they visualize power‑flow density and surface currents. At 1 GHz the measured crosstalk is about –52 dB, which appears tolerable for low‑speed links. However, at 10 GHz the coupling worsens to roughly –32 dB, and by 20‑30 GHz it reaches –25 dB, indicating that the victim trace begins to carry significant unwanted energy.
The speakers highlight that the coupling is not merely a static field overlap; it follows linear superposition and is highly dependent on the relative phase of the aggressor and victim signals. In‑phase signals amplify the combined field, while 180° out‑of‑phase signals can partially cancel, altering the eye diagram and noise floor. They liken dense orthogonal bus arrangements to unintentional directional couplers, turning a routing convenience into a source of signal degradation.
The practical takeaway for designers is clear: conventional SI solvers may miss this phenomenon, so full EM analysis is essential for high‑speed designs. Proper spacing, layer assignment, and awareness of bus density can prevent inadvertent coupling that would otherwise compromise data integrity, especially in multi‑gigabit applications.
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