EDA And IP Numbers Up Again, But Numbers Are More Nuanced
Electronic design automation (EDA) and semiconductor IP revenue rose 10.3% in Q4 2025, reaching $5.466 billion versus $4.955 billion a year earlier. The CAE segment led the growth, up 9.4% to $2.083 billion, while non‑reporting IP firms—dominated by Arm—jumped 24.7% to $1.413 billion. Reporting IP companies lagged, growing only 6.8% in the quarter and 3% over the past four quarters, and physical‑design revenue slipped 2.6%. Services revenue, however, surged 19.6% to $233.9 million.
Blog Review: Apr. 8
The April 8 blog roundup from Semiconductor Engineering spotlights a wave of technical breakthroughs across the semiconductor ecosystem. Cadence unveils LPDDR6 with built‑in metadata, row‑hammer mitigation and three‑rail DVFS, while Synopsys and Siemens champion multiphysics and simulation‑driven digital twins for automotive...
The Specialty Device Surge Part 2: The Process Control Challenges Of MEMS, Co-Packaged Optics, And More
The second installment of the Specialty Device Surge series highlights how MEMS, CMOS image sensors, SiC/GaN power devices, and co‑packaged optics are confronting unprecedented process‑control hurdles as wafer sizes expand to 300 mm. Each device family relies on unique materials—piezo films,...
Enhancing Silicon Reliability With In-System Test And SLM Data
The semiconductor industry is leveraging in‑system test (IST) and Silicon Lifecycle Management (SLM) data to boost chip reliability across design, manufacturing, and field operation. Traditional DFT methods such as ATPG, scan chains, and BIST remain core, but embedded monitors and...
Research Bits: Apr. 6
Researchers at Loughborough University unveiled a nanoporous niobium‑oxide memristor that performs reservoir computing directly in hardware, achieving up to 2,000‑times lower energy consumption than conventional software solutions. The same chip accurately forecasted short‑term Lorenz‑63 chaos, recognized pixelated digits and executed...
Developing A Security Framework For Chiplet-Based Systems
The article outlines a security framework for chiplet‑based systems, emphasizing that each chiplet must possess a verifiable identity tied to a platform‑wide trust chain. It describes two provisioning patterns—certificate‑based external provisioning and silicon‑derived (PUF) self‑generated keys—and explains how both feed...
Automated Multiphysics For Successful 3D-IC Design
Design teams moving to 3D‑IC architectures face intertwined power, thermal and mechanical challenges that can jeopardize yield and reliability. Traditional 2D verification tools fall short because stacked dies introduce new materials and complex inter‑dependencies. Siemens EDA’s Calibre 3DStress combined with...
AI Demand Resets Memory Market Priorities, Tightening NOR Flash Availability
The surge in AI infrastructure is creating a memory supercycle that pushes leading chipmakers to prioritize high‑margin products such as HBM, DDR5 and advanced NAND. DRAM prices are projected to jump roughly 90% quarter‑over‑quarter, while NAND could rise about 60%,...
World First: MACsec IP Receives ISO/PAS 8800 Certification For Automotive And Physical AI Security
Synopsys became the first company to earn ISO/PAS 8800 certification for its MACsec IP, a standard that secures Ethernet communication inside vehicles. The certification, validated by SGS TÜV Saar, confirms that the IP not only protects data integrity but also meets the...
Moving Electrons, Not Just Vehicles
The article examines how modern power electronics—especially multi‑level converters, silicon‑carbide (SiC) devices, and advanced power‑management ICs—are improving efficiency in electric vehicle (EV) and robot battery systems. It highlights fast‑charging challenges, noting that 15‑minute 0‑80% charges and 750 kW superchargers generate heat...
The One Bit Problem That Can Break a System
Bit flipping, once a rare reliability glitch, has become a systemic risk as semiconductor nodes shrink, clock speeds rise, and operating voltages drop, exposing aerospace, automotive and data‑center chips to silent data corruption. The phenomenon is driven by cosmic radiation,...
Embedded World 2026: Bringing Edge AI Into The Real World
At Embedded World 2026, Synaptics demonstrated that artificial intelligence is moving off the cloud and onto the device, delivering real‑time, context‑aware capabilities at the edge. The company showcased the SYN765x platform, which bundles Wi‑Fi 7, Bluetooth 6.0 and on‑chip AI compute for...
Secure at First Silicon: Reducing Cost and Risk
Side‑channel leakage often surfaces only after first silicon, forcing expensive redesigns. The Inspector Pre‑Silicon framework embeds side‑channel analysis into RTL and gate‑level verification, generating test vectors and statistical metrics to identify leakage early. By providing actionable, module‑level insights throughout the...
Causal Inference for AMS Design (U. Of Florida)
University of Florida researchers released a technical paper introducing a causal‑inference framework for analog‑mixed‑signal (AMS) circuit design. The method builds a directed‑acyclic graph from SPICE simulation data and estimates average treatment effects (ATE) to rank design parameters. Tested on three...
Integrating Error Propagation Theory Into the FMEDA Framework (Robert Bosch GmbH)
Robert Bosch GmbH released a technical paper that embeds error propagation theory into the FMEDA (Failure Modes, Effects, and Diagnostic Analysis) framework. The authors demonstrate how to calculate confidence intervals for the Single Point Fault Metric (SPFM) and Latent Fault...
In-Depth Analysis of 187 Publications on Hardware Reverse Engineering (Ruhr U., MPI)
A new Systematization of Knowledge paper from Ruhr University Bochum and the Max Planck Institute surveys 187 peer‑reviewed hardware reverse engineering (HRE) studies spanning ICs, FPGAs and netlists. The analysis reveals that only seven papers (4%) supplied reproducible artifacts, underscoring...
Systematic Analysis of CPU-Induced Slowdowns in Multi-GPU LLM Inference (Georgia Tech)
Georgia Tech researchers released a paper exposing how CPUs, not GPUs, often throttle multi‑GPU large language model (LLM) inference. Under‑provisioned CPU cores cause delayed kernel launches, stalled communication, and tokenization lag, leaving GPUs idle even when they have capacity. Adding...
Chip Industry Week In Review
Arm unveiled its first internally designed AGI CPU built on TSMC’s 3 nm process, targeting power‑efficient AI data‑center workloads. Gartner predicts inference costs for 1‑trillion‑parameter LLMs will fall more than 90 % by 2030, while Google warns quantum computers could break current...
AI Workloads Are Turning The Data Center Network Into A Combined Memory And Storage Fabric
AI inference is redefining data‑center networks, turning them into a unified memory‑and‑storage fabric. Unlike the bursty traffic of classic microservices or training workloads, inference generates sustained, high‑volume data flows to fetch KV‑cache state from remote memory and flash. This shift...
Importance Of Hardware Security Verification In Pre-Silicon Design
Hardware security verification is becoming a prerequisite for any silicon destined for cloud, automotive, industrial or edge AI applications. The discipline rests on two pillars: functional security verification, which confirms that security features behave as specified, and protection verification, which...
Memory Wall Gets Higher
SRAM scaling has stalled, causing the memory wall to rise as each new node shrink consumes a larger chip fraction without delivering proportional capacity or speed gains. The issue now affects not only cutting‑edge AI accelerators but will eventually impact...
Precision In Depth: Extraction Workflows For CFETs And Buried Power Rails
Chip designers are turning to complementary field‑effect transistors (CFETs) and buried power rails (BPRs) to extend Moore’s Law beyond the 5 nm barrier. By stacking n‑ and p‑type devices vertically and routing power beneath the active layers, these architectures double density...
Detect, Diagnose, And Debug Using Sensors And Functional Monitoring
Modern AI accelerators generate nanosecond‑scale current spikes that push on‑die power delivery networks (PDN) beyond their voltage limits, capping computational throughput. Rack power density is soaring toward 100 kW, creating transient load spikes that traditional power infrastructure cannot absorb. Siemens Tessent Embedded...
Removing The Accuracy And Time Tradeoff In EM Simulation
For years engineers balanced electromagnetic FEM accuracy against long solve times, especially as frequencies surpassed 60 GHz and meshes grew. Keysight’s Advanced Design System now embeds NVIDIA’s cuDSS sparse direct solver, running on H100 GPUs, to accelerate FEM linear solves. Benchmarks...
AI Won’t Kill Verification IP, But It Will Redefine It
Verification IP (VIP) remains essential as chip designs move to 3nm and 2nm nodes, accounting for roughly 68% of the development cycle. AI tools are poised to augment VIP by automating test generation, integration, and debug, rather than replacing the...
Beating The Heat In 3D Packages
Thermal management has become a top‑level constraint for 3D multi‑die packages as power densities exceed 1 kW. Engineers are adopting AI‑driven adaptive meshing and real‑world test wafers to bridge simulation and measurement, while system‑level technology co‑optimization (STCO) strategies have cut GPU...
Auto Ethernet 10BASE-T1s Steps Up, With Tbps On The Horizon
Automotive Ethernet, especially the 10BASE‑T1S single‑pair standard, is emerging as the primary replacement for the legacy CAN bus in modern vehicles. While 10 Mbps meets current low‑speed needs, OEMs are already planning higher‑speed links—25 Gbps, 100 Gbps, and eventually terabit per second—to support...
How SW and HW Vulnerabilities Can Complement LLM-Specific Algorithmic Attacks (UT Austin, Intel Et Al.)
A collaborative paper titled “Cascade” reveals how conventional software and hardware flaws can be weaponized alongside LLM‑specific algorithmic attacks to compromise compound AI pipelines. The authors demonstrate two proof‑of‑concept attacks: a code‑injection combined with a Rowhammer guardrail bypass that injects...
Bias- and Temperature-Dependent Noise Measurements to Investigate Carrier Transport at the Tellurium Interface (POSTECH)
Researchers at POSTECH have identified contact‑origin trap‑assisted tunneling as the dominant source of low‑frequency noise in ultrathin (5 nm) tellurium field‑effect transistors at room temperature. Temperature‑dependent 1/f noise measurements reveal that cooling to 100 K suppresses trap activation, restoring the carrier‑number‑fluctuation (CNF)...
Liquid Cooling Drives Other Localized Cooling
Liquid cooling is increasingly used to manage high‑power GPUs and AI chips, but removing traditional airflow can leave nearby components overheating. Engineers must perform whole‑board thermal analysis to identify chips that transition from warm to hot without liquid cooling. Alternative...
Advanced Packaging Limits Come Into Focus
Advanced packaging has become the primary performance variable for AI and HPC chips, with substrate, bonding, and process sequence dictating scalability. Engineers now face warpage, glass fragility, hybrid‑bond yield, and substrate limits as the dominant yield‑killers as packages grow larger...
Identifying Read Disturbance Threshold of DRAM Chips (ETH Zurich, Rutgers)
A paper titled “DiscoRD” from ETH Zurich and Rutgers introduces a rapid experimental method to determine the read‑disturbance threshold (RDT) of DDR4 DRAM chips. The authors measured hundreds of thousands of rows across 212 chips, building an empirical model of...
Analysis of the Evolving Landscape of Ultra-Low-Power Edge AI Processors (U. Of Austria, ETH Zurich)
A new arXiv paper from the University of Austria and ETH Zurich benchmarks ultra‑low‑power edge AI processors across three architectures: the RISC‑V‑based GAP9, the ARM Cortex‑M55 STM32N6, and Sony's in‑sensor IMX500. The study evaluates latency, inference efficiency, energy use, and...
AI Design Reshapes Data Management
Integrating AI into semiconductor design is compelling companies to revamp data management, moving from passive file repositories to active, machine‑readable data lakes enriched with metadata and ontologies. The surge in training and inference workloads makes data movement, congestion, and energy...
HBM4E Raises The Bar For AI Memory Bandwidth
Rambus unveiled HBM4E, the latest high‑bandwidth memory that doubles HBM4’s data rate to 16 Gbps per pin, delivering up to 24.6 TB/s aggregate bandwidth across a six‑device stack. The new standard retains HBM’s low‑power, low‑latency characteristics while expanding channel count to 32...
Rethinking Voice AI At The Edge: A Practical Offline Pipeline
Arm and NVIDIA unveiled an offline, real‑time voice AI pipeline on the DGX Spark platform, combining the faster‑whisper speech‑to‑text engine with the vLLM large‑language‑model server. The heterogeneous design assigns latency‑critical transcription to Arm Cortex‑X/A CPU cores while the GPU handles...
Serial Wire Debug (SWD) Protocol: Efficient Debug Interface For Arm-Based Systems
The Serial Wire Debug (SWD) protocol offers a two‑pin alternative to traditional JTAG, delivering high‑speed debug access for Arm Cortex‑M based SoCs. By using a single clock (SWCLK) and a bidirectional data line (SWDIO), SWD halves the pin count while...
AI Power on the Edge
Edge AI is reshaping device design by making power and thermal constraints primary, not optional, considerations. Engineers must build hardware architectures from the ground up and adopt a hardware‑software‑model co‑design approach to meet milliwatt budgets and fanless thermal envelopes. Memory...
Scale-Up, Scale-Out Get a New Partner
The article outlines three AI‑focused data‑center scaling models—scale‑up (in‑rack, latency‑centric, copper‑based), scale‑out (inter‑rack, jitter‑centric, RDMA and optical), and the newer scale‑across (cross‑data‑center, long‑distance congestion management). It details how each approach uses distinct interconnect strategies and resource allocation methods, and cites...
Customizing Foundation IP For Ultra-Low-Voltage Designs
Synopsys customized its Foundation IP to enable an ultra‑low‑voltage (0.4 V) optical networking chip designed for edge AI workloads. The team created a new memory compiler, added dual‑rail voltage support, and applied power‑gating and low‑leakage cells to meet aggressive power‑performance‑area (PPA)...
Neuromorphic Computing Platform In Perovskite Nickelates (UCSD, Rutgers)
Researchers at UCSD and Rutgers have demonstrated a neuromorphic computing platform built from proton‑doped perovskite nickelate (NdNiO3) devices. By integrating symmetric and asymmetric junctions on a single wafer, the system combines ultrafast proton‑mediated dynamics with multilevel resistance memory, achieving nanosecond...
Accelerating 4D Imaging Radar with Vision 4DR
Cadence introduced a 4D imaging radar solution that couples its Vision 341 DSP with the Vision 4DR accelerator to handle the heavy FFT workload inherent in high‑resolution MIMO radars. Adding elevation to range, velocity and azimuth creates a massive data...
The Specialty Device Surge Part 1: Wafer Size Transitions Are Powering The Future Of Specialty Devices And Bringing New Challenges
Specialty devices—including SiC and GaN power transistors, MEMS, photonics, and CIS—are shifting from traditional 150mm and 200mm wafers to larger 200mm and 300mm formats. GaN power is moving to 300mm, while SiC power advances to 200mm, and photonics, MEMS, and...
Enabling Seamless Monitoring, Test, And Repair In Multi-Die Designs
The semiconductor industry is turning to 2.5D/3D multi‑die designs to meet AI‑driven performance and efficiency goals. However, testing, monitoring, and repairing hidden chiplets remain a major hurdle. Synopsys and TSMC showcased a demo vehicle built on TSMC’s N3P process that...
The Petabyte Problem: How AI Is Finally Making Semiconductor Manufacturing Data Actionable
Semiconductor manufacturers are grappling with petabyte‑scale data from probe, assembly and test operations, yet less than 5% is currently used for analytics. PDF Solutions introduced its Exensio platform, combining a parallel data architecture, semantic integration, and agentic LLM capabilities to...
Ensuring AI Reliability: Mitigating OCP’s Silent Data Corruption Risks
An Open Compute Project whitepaper, co‑authored by NVIDIA, Google, Meta and Microsoft, warns that silent data corruption (SDC) is escalating in AI data centers as process geometries shrink and workloads intensify. SDC originates from timing violations, voltage‑frequency scaling, and wear‑out,...
Detecting Chemical Variability At Advanced Nodes
Advanced‑node semiconductor yield is increasingly eroded by subtle chemical variability in thin films, interfaces, and residues rather than obvious particle defects. This molecular variability manifests as parametric drift and margin erosion that only appear under workload or thermal stress, making...
Research Bits: Mar. 9
Researchers at UNIST unveiled a 28 nm injection‑locked clock multiplier that delivers 2.1 GHz signals with a record‑low -81.36 dBc reference spur and 280.9 fs jitter while consuming just 12.28 mW. A multinational team demonstrated a 2D‑material thermal sensor that reads temperature in 100 ns, is...
The Future of Semiconductors: Engineering in the Convergence Era
The semiconductor sector is moving into a convergence era where silicon, software, physics, packaging, security, AI and power constraints intersect. While transistor scaling remains relevant, architecture, integration, verification and automation now drive growth. System‑level engineering, digital twins and software‑defined chips...