The Memory Guy

Is a 96% Lower-Power NAND Coming?

Samsung researchers demonstrated a ferroelectric transistor that can cut NAND flash power consumption by up to 96%, integrating it into planar and 3‑D NAND strings. The approach replaces the traditional polysilicon channel or charge‑trap layer with a hafnium‑based ferroelectric oxide, reducing channel resistance and enabling lower write energy. The proof‑of‑concept, published in Nature, shows both planar and stacked 3‑D cells operating at dramatically lower voltage. Commercial adoption will depend on scaling, cost and manufacturing integration.