RISC-V Technical Session | From RISC-V Cores to Neuromorphic Arrays

Why It Matters

Open‑source RISC‑V neuromorphic cores lower entry barriers, enabling rapid prototyping and potentially delivering power‑efficient AI hardware for edge applications.

Key Takeaways

• RISC‑V can serve as foundation for neuromorphic processors
• Digital neuromorphic designs trade area for power efficiency
• Time‑multiplexed neuron cores reduce silicon but increase control overhead
• Open‑source RISC‑V cores enable rapid student prototyping for neuromorphic research
• Programmable synaptic memory is essential for general‑purpose neuromorphic chips

Summary

Dr. Amir Yusada, an assistant professor at the University of Twente, presented a technical session on leveraging RISC‑V cores to construct neuromorphic arrays. Drawing on his experience in digital hardware, startups, and research institutes, he highlighted a new open‑source tutorial that lets master‑level students build simple neuromorphic processors using familiar RISC‑V tools.

The talk emphasized the brain’s ultra‑low power operation—approximately 10 µW for a fruit‑fly brain with over 140,000 interconnected neurons—and how that efficiency stems from sparse, event‑driven, distributed processing with collocated compute and memory. Yusada argued that digital implementations can capture these principles, though they sacrifice area for power. He described common design patterns: tiny processing elements with programmable synaptic memories, cross‑bar interconnects, and aggressive time‑multiplexing of neurons to curb silicon usage, acknowledging the resulting control overhead.

Concrete examples included his stint at Gray Matter Labs, where the team replaced custom neuron processors with a minimal RISC‑V CPU to gain flexibility, and the open‑source tutorial that now enables students to prototype neuromorphic chips without NDAs. He also referenced the broader debate between analog, mixed‑signal, and emerging device approaches, noting that a fully digital RISC‑V foundation can later be augmented with analog or novel devices.

The implications are clear: an open, RISC‑V‑based stack democratizes neuromorphic hardware development, accelerates academic and industry experimentation, and could spur a new class of ultra‑low‑power AI accelerators. By addressing system‑level bottlenecks—programmable memory, interconnect topology, and efficient time‑multiplexing—researchers can focus on algorithmic innovations without reinventing the silicon substrate.

Original Description

This talk presents a research journey from energy-efficient RISC-V processor design toward neuromorphic computing architectures for embedded AI. It highlights how principles from digital hardware design, processor architecture, and hardware/software co-design can be applied to build scalable, efficient neuromorphic systems.

Presenter: Amir Yousefzadeh, University of Twente, Assistant Professor

Dr. Amir Yousefzadeh is an Assistant Professor at the University of Twente, the Netherlands, where he works on embedded AI, computer architecture, and neuromorphic systems. His research focuses on the design of energy-efficient hardware and algorithms for intelligent edge devices, with emphasis on neuromorphic computing, RISC-V-based architectures, and hardware/software co-design for AI workloads.