Hall Switch Streamlines Automotive Position Sensing
Melexis introduced the MLX92344, a 2‑wire, 2‑bit Hall‑effect switch that can detect up to four positions in automotive body electronics. The device replaces multiple mechanical microswitches by offering programmable current levels (3 mA‑28 mA) and magnetic thresholds across a 0.5‑200 mT range. It operates from 2.7 V to 28 V, –40 °C to +150 °C, and meets ASIL B SEooC and AEC‑Q100 qualifications. Available in surface‑mount and through‑hole packages, it can be read via standard I/O triggers or an ADC.
NVIDIA Chip Powers Local AI Workloads
NVIDIA unveiled the RTX Spark, a super‑chip delivering up to one petaflop of AI compute for Windows PCs. It pairs a Blackwell RTX GPU with 6,144 CUDA cores, fifth‑generation Tensor Cores, and 128 GB unified memory, linked via NVLink‑C2 to a 20‑core...
How Fleet Learning Works Under Bounded Gate Authority
The third article in the silicon‑governance series explains how fleet learning must operate under bounded gate authority. Fleet learning aggregates field telemetry to spot macro‑scale failure signatures, structural drift, and systemic patterns across AI accelerators, chiplets, and data‑center clusters. However,...
The Hidden Bottleneck in LLM Inference and the Impact on MLPerf Benchmarking
Recent LLM inference benchmarks reveal that GPUs excel at the prefill phase but falter when real‑time token generation is required. The generation step is sequential and memory‑bound, causing utilization to collapse as batch sizes shrink for low‑latency serving. Disaggregating workloads—dedicating...
Agilex 9 FPGAs Power COTS VPX Boards
Altera has teamed with Mercury Systems and VadaTech to embed its Agilex 9 medium‑band Direct RF FPGAs into commercial‑off‑the‑shelf VPX boards. The Mercury DRF5660 and VadaTech VPX540 modules, both OpenVPX/SOSA‑compliant, are now available for immediate order. Agilex 9 combines RF data converters, high‑speed...
From AI Silicon Observability to Governed Evidence
AI silicon performance now hinges on internal data movement managed by network‑on‑chip (NoC) architectures, but NoC activity alone cannot establish root‑cause of system symptoms. SEGA‑AI introduces a governance layer that qualifies observability data into admissible evidence before any corrective decision...
A Closer Look at Huawei’s Chip Design Workaround without EUV
Huawei unveiled a new chip design strategy called LogicFolding, which relies on 3D stacking and aggressive hybrid bonding to sidestep the need for extreme‑ultraviolet (EUV) lithography. The approach targets a 1.4 nm process node slated for 2031, positioning the company to...
AI Augments Advances in Medical Electronics
Artificial intelligence is reshaping medical electronics, especially diagnostic imaging, wearables, and implantables. The market is projected to reach $11.9 billion by 2026, growing at 6.7% CAGR, while more than 600 AI‑enabled devices earned FDA clearance by mid‑2024. AI accelerates image analysis,...
AI-Powered Medical Imaging: Turning Data Into Faster Diagnoses
AI is transforming the medical imaging workflow—from exam ordering to final interpretation—by embedding deep‑learning models such as CNNs, U‑Net and emerging Vision Transformers. The technology speeds acquisition, enables low‑dose CT reconstruction, and reduces MRI scan times by up to 75%...
MCUs Bridge I3C Across Voltage Domains
Microchip has launched the PIC18‑Q20 family of 8‑bit MCUs that embed up to two I3C peripherals and Multi‑Voltage I/O (MVIO) in ultra‑compact 14‑ and 20‑pin packages as small as 3 × 3 mm. The devices operate across three independent voltage domains, with MVIO‑enabled...
Motor MCU Integrates Driver and Control Functions
Toshiba has begun sampling the TB9M040FTG, a motor‑control device that merges an Arm Cortex‑M23 MCU with a 2 A three‑phase brushless‑DC driver. The part, part of the SmartMCD series, adds flash memory, a 5‑V high‑side driver, LIN transceiver and a hardware...
CPU IP Processes Mixed Scalar and Vector Workloads
SiFive unveiled its Performance P570 Gen 3, a RISC‑V out‑of‑order superscalar processor IP that blends scalar and vector execution. The chip promises a sizable performance uplift over the earlier P550 Gen 1 and complies with the mandatory RVA23 profile, including Hypervisor and...
How Data Movement Defines Performance for AI Silicon
AI silicon performance now hinges on efficient data movement rather than raw compute power. In data‑center GPUs, over 80% of dynamic energy is spent shuttling data to DRAM, while edge AI devices can waste up to 90% of inference time...
GPUs: A High-Throughput Architecture Confronting a Workload Shift
Graphics processing units still power large‑scale AI training, but frontier large language models are exposing a growing memory bottleneck. While Nvidia H100 GPUs can deliver petaflops of FP8 throughput, trillion‑parameter inference often falls below 10 FLOPs per byte, making bandwidth...
4D Vision Platform Enhances Perimeter Monitoring
SiLC unveiled the Eyeonic Vista, a high‑resolution 4D vision platform that combines 1550‑nm FMCW LiDAR with micro‑Doppler velocity data to detect and classify objects beyond 1 km. The system delivers angular resolution as fine as 0.008°, dynamic ROI scaling, and dual‑polarization...