Hardening the Silicon: Why Analog Anti-Tamper IP Is the New Security Baseline
Analog anti‑tamper IP is emerging as a baseline for hardware security as billions of IoT and automotive SoCs face increasingly sophisticated physical attacks. Hackers now employ fault injection, glitching, side‑channel, and micro‑probing techniques that can bypass software‑only protections and compromise the Root of Trust. Analog sensors—monitoring voltage, clock, temperature, and electromagnetic disturbances—provide real‑time detection and can trigger key‑zeroization or resets. Agile Analog’s Composa tool automates the creation of such analog IP across any foundry, shortening development cycles and lowering costs.
Renesas Scalable Automotive SoC Design Using Arteris NoC
Renesas has integrated Arteris FlexNoC interconnect IP into its next‑generation Gen‑5 R‑Car automotive SoCs. The NoC fabric links Arm CPU clusters, GPUs and neural‑processing accelerators, delivering scalable bandwidth and deterministic QoS for advanced ADAS and autonomous‑driving workloads. Power consumption drops...
Calibrating Quantum Computing Activity in Financial Services
At a Fujitsu‑hosted event, senior technologists from Fujitsu, HSBC and industry analysts discussed the realistic state of quantum computing in financial services. The consensus was that while quantum offers promise for probabilistic modeling, optimization and quantum‑machine‑learning, hardware is still years...
NoC Matters: Designing the Backbone of Next-Gen AI SoCs
The article argues that network‑on‑chip (NoC) design has become the cornerstone of modern AI‑centric System‑on‑Chips, dictating performance, power efficiency, and scalability. As heterogeneous accelerators proliferate, data movement dominates system behavior, making NoC topology, buffering, and QoS policies critical. Designers must...
From Wooden Boards to White Gloves: How FPGA Prototyping and Emulation Became Two Worlds of Verification… and How the Convergence...
FPGA prototyping and hardware emulation originated from parallel needs—speed and system realism versus deep debugging of ever‑larger designs. Prototyping leverages re‑programmable silicon to run software workloads early, while emulation provides controlled, observable execution for complex verification. Historically served distinct vendor...
CEO Interview with Dr. Hardik Kabaria of Vinci
Vinci, led by founder‑CEO Dr. Hardik Kabaria, has deployed the first production‑grade physics foundation model that continuously computes thermal and mechanical behavior directly on semiconductor geometry. The deterministic, solver‑accurate platform replaces episodic simulation with an always‑on engine, delivering up to...
CEO Interview with Steve Kim of Chips&Media
Chips&Media CEO Steve Kim highlighted that the Seoul‑based multimedia IP firm powers more than 3 billion devices for over 150 top‑tier customers. The company’s portfolio now spans high‑efficiency 8K video codecs, AI‑focused image‑processing NPUs and advanced Frame Buffer Compression (FBC) technology....
YieldHUB Expands Its Impact with New Technology and a New Website
YieldHUB has launched a redesigned website and introduced YieldHUB Live, a real‑time manufacturing intelligence layer for semiconductor test floors. The new portal groups solutions by product lifecycle, device architecture and user role, while the live platform delivers continuous visibility, anomaly...
NXP Expands Arteris NoC Deployment to Scale Edge AI Architectures
NXP announced an expanded deployment of Arteris’s NoC and cache‑coherent IP suite—including FlexNoC®, Ncore®, CodaCache® and the Magillem® integration platform—across its upcoming edge‑AI silicon. The move targets the growing need for deterministic latency, high bandwidth, and safety‑critical isolation in heterogeneous...
Architecting Intelligence: The Rise of RISC-V CPUs in Agentic AI Infrastructure
SiFive announced a $400 million Series G round that lifts its valuation to $3.65 billion, earmarked for next‑generation RISC‑V CPU IP aimed at agentic AI data‑center workloads. The funding will accelerate hardware co‑design that tightly integrates scalar, vector and matrix compute units to...
Intel, Musk, and the Tweet That Launched a 1000 Ships on a Becalmed Sea
Intel announced a partnership with Elon Musk’s Terafab project, joining SpaceX, xAI and Tesla to develop a 1‑terawatt‑per‑year AI compute fab. The deal follows Intel’s $11.1 billion federal rescue, converting unspent grants into a 9.9% U.S. government equity stake. Musk’s ecosystem...
From SoC to System-in-Package: Transforming Automotive Compute with Multi-Die Integration
Automotive electronics are moving from monolithic system‑on‑chips to multi‑die system‑in‑package solutions to meet soaring compute, safety, and longevity demands. By stacking or side‑by‑side heterogeneous dies, manufacturers can combine CPUs, GPUs, AI accelerators and high‑bandwidth memory within a single package. This...
An Upper Bound on Effective Quantum Computation?
A recent PNAS paper argues that a fundamental limit exists on how many qubits can be meaningfully entangled, estimating an upper bound of roughly 1,000 logical qubits. The limit stems from a proposed discretization of space, which restricts the range...
YieldWerx Delivers a Master Class in Co-Packaged Photonics Implementation
YieldWerx announced a forthcoming webinar that will teach semiconductor engineers how to implement co‑packaged photonics (CPO) across the full product lifecycle. The session, led by CEO/CTO Aftkhar Aslam, will detail the 12 cross‑domain challenges—from optical data complexity to test‑flow discontinuities—and...
RISC-V Has Momentum. The Real Question Is Who Can Deliver
RISC‑V has moved from a promising ISA to a viable platform as the RVA23 baseline unifies high‑performance compute. Arm’s recent transition to a silicon‑first model reshapes the IP landscape, intensifying competition. Akeana’s Alpine test chip, taped out in a 4 nm...
