Recent Posts
News•Feb 22, 2026
CEO Interview with Juniyali Nauriyal of Photonect
Photonect, a Rochester‑based photonics startup founded by CEO Juniyali Nauriyal, is commercializing a laser‑fusion, epoxy‑free fiber‑to‑chip attachment process. The technology, built around an oxide mode converter, lifts coupling efficiency from roughly 50 % to 80 % and cuts optical loss to under 1 dB. By forming glass‑to‑glass bonds in under a minute, it boosts throughput tenfold and halves per‑device cost. The company will debut its high‑volume PIX‑Attach system at OFC 2026, targeting AI data centers, HPC, telecom and quantum markets.
By SemiWiki
News•Feb 20, 2026
What Is the 3nm Pessimism Wall and Why Is It An Economic Crisis?
The article defines the “3 nm Pessimism Wall” as the excessive 25‑35% clock‑period guard bands that arise from abstraction‑based sign‑off methods rather than physical limits. These inflated margins force over‑design of buffers, increase power consumption, and waste silicon area, turning advanced‑node...
By SemiWiki
News•Feb 20, 2026
CEO Interview with Aftkhar Aslam of yieldWerx
YieldWerx, led by semiconductor veteran Aftkhar Aslam, offers a data‑centric yield‑analytics platform that consolidates fragmented fab, test, and packaging information into a single, actionable environment. The solution tackles extreme data volumes and multi‑domain complexity, supporting advanced packaging, silicon photonics, MicroLED,...
By SemiWiki
News•Feb 19, 2026
Intelligent Networks: Power, Reliability, and Maintenance in Telecom — Webinar Preview
The upcoming webinar "Intelligent Networks: Power, Reliability, and Maintenance in Telecom" will explore how telecom operators can leverage AI, real‑time analytics, and automation to tackle rising energy costs, ensure ultra‑reliable service, and modernize maintenance. It highlights the shift toward cloud‑native,...
By SemiWiki
News•Feb 19, 2026
LUBIS EDA: Addressing the Verification Bottleneck in Modern Chip Design
Verification has become the primary bottleneck in modern chip design, as simulation struggles to cover the exponential state space of AI, HPC, and automotive processors. Formal verification offers exhaustive proof of design properties but traditionally required manual assertions and specialist...
By SemiWiki
News•Feb 17, 2026
Ceva IP: Powering the Era of Physical AI
Ceva IP is positioning itself as the core enabler of Physical AI, delivering integrated semiconductor and software IP that brings sensing, connectivity, and on‑device inference to edge devices. By moving AI processing from the cloud to the chip, its solutions...
By SemiWiki
News•Feb 17, 2026
Accelerating Static ESD Simulation for Full-Chip and Multi-Die Designs with Synopsys PathFinder-SC
Synopsys unveiled PathFinder‑SC, a static ESD verification platform that enables early, layout‑driven analysis for full‑chip and multi‑die designs. Leveraging cell‑based modeling from GDS/DEF data and the Seascape distributed‑computing engine, the tool can simulate billions of nodes and complete complex resistance...
By SemiWiki
News•Feb 17, 2026
A Century of Miracles: From the FET’s Inception to the Horizons Ahead
2025 marks the centennial of the field‑effect transistor, first patented by Julius Lilienfeld in 1925. After decades of material and physics challenges, MOSFET stability was achieved in 1969, launching the era of large‑scale integration and the scaling roadmap defined by...
By SemiWiki
News•Feb 16, 2026
Two Open RISC-V Projects Chart Divergent Paths to High Performance
Two open‑source RISC‑V projects—ETH Zürich’s Ara vector processor and China’s XiangShan scalar core—demonstrate opposite strategies for scaling performance. Ara implements the RISC‑V Vector Extension with explicit parallelism and no speculation, relying on software‑managed locality and a shallow memory hierarchy. XiangShan...
By SemiWiki