Bias- and Temperature-Dependent Noise Measurements to Investigate Carrier Transport at the Tellurium Interface (POSTECH)

Why It Matters

The work provides a practical pathway to decouple device scaling from noise penalties, crucial for reliable, low‑noise tellurium‑based electronics and BEOL‑compatible integration.

Key Takeaways

• 5 nm Te FETs show contact‑origin trap noise at 300 K
• Cooling to 100 K restores carrier‑number‑fluctuation behavior
• 13 nm Te devices screen traps, maintain CNF across temperatures
• Thickened contact layer cuts noise by tenfold, halves bias dependence
• Engineering contacts decouples scaling from noise in Te transistors

Pulse Analysis

Tellurium’s narrow bandgap, air stability, and high hole mobility have positioned it as a leading p‑type material for next‑generation ultrathin electronics. Yet, when the channel thickness approaches the depletion width, interface traps at the metal contacts become a critical bottleneck, injecting excess low‑frequency 1/f noise that degrades signal integrity. Understanding the microscopic origins of this noise is essential for designers seeking to push Te transistors into sub‑10 nm regimes while maintaining performance benchmarks comparable to silicon and other 2‑D semiconductors.

In a systematic bias‑ and temperature‑dependent study, POSTECH researchers demonstrated that 5 nm tellurium FETs deviate from the conventional carrier‑number‑fluctuation (CNF) model at 300 K, indicating trap‑assisted tunneling dominates the noise spectrum. Cooling the devices to 100 K quenches trap activation, allowing CNF behavior to re‑emerge, while 13 nm channels inherently screen the contact region, preserving CNF across the temperature range. These findings pinpoint near‑contact traps as the primary culprits, offering a clear diagnostic metric for future device optimization.

Armed with this insight, the team engineered a locally thickened tellurium layer beneath the source and drain contacts, effectively isolating the active 5 nm channel from trap‑rich interfaces. This simple yet powerful modification lowered the noise floor by roughly tenfold and reduced its dependence on drain bias by about 50 %. The approach decouples aggressive scaling from noise penalties, paving the way for reliable, low‑noise Te‑based circuits that can be integrated directly into back‑end‑of‑line (BEOL) processes. As the semiconductor industry seeks alternatives to silicon for niche high‑performance applications, such contact‑centric engineering could accelerate the commercial adoption of tellurium electronics.