CEA‑Leti to Showcase Integrated Expertise in Microelectronics Reliability at IRPS 2026

Why It Matters

The findings provide actionable reliability data that de‑risk next‑generation RF, power and 3‑D integration platforms, shortening time‑to‑market for high‑performance semiconductor products.

Key Takeaways

• Seven papers showcase CEA‑Leti’s breadth in reliability research
• New RF methodology measures hot‑carrier lifetime under realistic stress
• GaN‑on‑Si MIS‑HEMTs remain stable after 1,400 h at 375 °C
• Low‑temperature BEOL flow achieves 10‑year BTI target
• Spacer material selection crucial for FD‑SOI hot‑carrier endurance

Pulse Analysis

The International Reliability Physics Symposium (IRPS) 2026 will serve as a showcase for cutting‑edge microelectronics reliability research, and CEA‑Leti is positioned at the centre of the program with seven peer‑reviewed papers. The institute’s portfolio spans device physics, process integration, RF, FD‑SOI, GaN, BEOL, and low‑temperature 3‑D sequential platforms, reflecting a holistic approach that couples advanced characterization with physics‑based modeling. By presenting both experimental data and calibrated simulation tools, CEA‑Leti provides the industry with early‑stage reliability insights that can be fed directly into design‑for‑reliability (DfR) flows, shortening the time from lab to fab.

Among the highlighted contributions, a novel RF methodology directly measures hot‑carrier‑induced lifetime of SOI power amplifiers under realistic bias and load‑impedance conditions, delivering contour maps that guide mmWave 5G PA design. In parallel, a CMOS‑compatible GaN‑on‑Si MIS‑HEMT demonstrated only modest threshold shift and contact‑resistance increase after 1,400 hours at 375 °C, confirming its suitability for high‑temperature automotive and aerospace power blocks. A low‑temperature BEOL flow, using Si‑poly gates and UV‑laser anneal, met the 10‑year BTI target for 2.5 V high‑voltage CMOS, enabling reliable stacking in 3‑D sequential processes. These results collectively lower the risk envelope for next‑generation RF, power, and 3‑D integration technologies.

The broader impact of CEA‑Leti’s findings lies in accelerating industrial readiness of emerging platforms such as GaN power electronics, FD‑SOI logic, and 3‑D sequential CMOS image sensors. By quantifying degradation mechanisms—from hot‑carrier and bias‑temperature instability to electromigration and random‑telegraph noise—the institute equips designers with predictive models that reduce costly silicon iterations. As automotive, aerospace, and 5G ecosystems demand higher performance at harsher temperatures, these reliability‑aware innovations will shape product roadmaps and reinforce Europe’s leadership in semiconductor technology.