CEA-Leti, CEA-List and PSMC Collaborate to Integrate RISC-V and MicroLED Silicon Photonics Into 3D Stacking and Interposer for Next-Generation AI

Why It Matters

The integration of RISC‑V and microLED photonics into 3D stacking delivers higher data throughput with lower power, a critical need for AI accelerators. This breakthrough could reshape semiconductor roadmaps by enabling more flexible, cost‑effective AI hardware.

Key Takeaways

• RISC‑V IP integrated into PSMC 3D stacking
• MicroLED silicon photonics enable low‑power optical links
• High‑bandwidth interconnects address copper scaling limits
• Customizable RISC‑V cores reduce AI compute power
• PSMC offers foundry services for AI chiplets

Pulse Analysis

The semiconductor sector is confronting a convergence of physical and economic pressures: copper interconnects are nearing their bandwidth ceiling, power budgets are tightening, and AI workloads demand ever‑greater data movement. Silicon‑photonic microLED links provide a compelling alternative, delivering short‑reach optical channels that consume far less energy per bit than traditional metal lines. By embedding these links directly into 3D‑stacked interposers, manufacturers can sustain scaling trends without incurring the thermal penalties that have plagued conventional approaches.

RISC‑V’s open‑source architecture adds a complementary layer of flexibility to the hardware stack. Designers can tailor instruction sets, pipeline depths, and peripheral integrations to match specific AI inference or training profiles, reducing unnecessary silicon and cutting power consumption. CEA‑List’s expertise in crafting bespoke RISC‑V cores means that PSMC’s customers will receive compute engines that are not only high‑performance but also optimized for the photonic communication fabric, creating a tightly coupled compute‑to‑data pipeline that maximizes efficiency.

For PSMC, the collaboration expands its foundry service portfolio beyond pure packaging into a full‑stack AI solution provider. By offering ready‑made chiplet ecosystems that combine RISC‑V compute with microLED‑based photonic interconnects, the company can attract AI chip designers seeking rapid time‑to‑market and lower development costs. This move signals a broader industry shift toward heterogeneous integration, where specialized IP blocks communicate over optical links, setting a new benchmark for next‑generation AI hardware performance.