PDN Challenges In DRAM-Based Compute-In-Memory Systems (UT Austin)

Why It Matters

Understanding PDN constraints is critical for bringing DRAM‑based PIM from research labs to data‑center and edge deployments, where power integrity directly impacts performance and yield. The paper’s taxonomy and mitigation roadmap give chip designers actionable guidance to avoid costly redesigns.

Key Takeaways

• PIM introduces bursty, localized current spikes stressing DRAM PDN
• Voltage droop and IR drop can cause reliability failures
• Timing constraints and controller scheduling mitigate PDN stress
• Data placement and bank‑level power management reduce thermal hotspots
• Unified taxonomy guides future PDN‑aware PIM designs

Pulse Analysis

Compute‑in‑memory (PIM) has emerged as a promising solution to the memory wall, allowing data‑intensive workloads to execute where data resides. DRAM, with its high density and mature fabrication ecosystem, is a natural substrate for PIM, enabling techniques such as multi‑row activation and near‑bank compute units. However, these innovations alter traditional current draw patterns, turning the memory module into a dynamic power hotspot that challenges the power delivery network (PDN). The resulting voltage droop and IR drop not only degrade performance but also threaten long‑term reliability, especially as manufacturers push toward higher bandwidth and larger parallelism.

The UT Austin paper tackles this issue by presenting a unified taxonomy that maps PIM‑induced current behavior along two axes: temporal (burst versus sustained) and spatial (localized versus distributed). This framework clarifies why certain PIM approaches, like simultaneous activation of multiple subarrays, generate sharp, localized current surges, while others produce more distributed, sustained loads. By quantifying these patterns, designers can predict PDN stress points, anticipate thermal hotspots, and evaluate trade‑offs between computational density and power integrity.

Armed with this insight, the authors propose a suite of mitigation strategies that leverage existing DRAM architecture. Adjusting timing constraints, fine‑tuning memory‑controller scheduling, and strategically placing data across banks can smooth out current peaks. Additionally, bank‑ and vault‑level power management schemes help dissipate heat and maintain voltage margins. For industry players eyeing commercial PIM products, these recommendations provide a practical roadmap to scale DRAM‑based compute without compromising yield, positioning PIM as a viable accelerator for AI, analytics, and high‑performance computing workloads.