Practical Design Guidelines for Atom-Thin Oxide Transistors Enable Reliable 3D Chip Integration

Why It Matters

The framework turns costly trial‑and‑error into a predictive design tool, accelerating the adoption of ultrathin oxide transistors for energy‑efficient 3D integrated circuits.

Key Takeaways

• Unified model links thickness, traps, interface, roughness.
• Tungsten-doped In2O3 reduces leakage and improves interface.
• Predictive design replaces trial‑and‑error for 3D stacking.
• Model works from 2 nm to 13 nm channels.
• Enables low‑temperature (<400 °C) back‑end transistor fabrication.

Pulse Analysis

Three‑dimensional chip stacking is reshaping semiconductor manufacturing, but it places stringent demands on the transistors that sit atop existing layers. They must be fabricated at low temperatures, remain only a few nanometers thick, and consume minimal power while delivering reliable switching. Oxide semiconductors, especially indium‑oxide, have emerged as promising candidates because they can be processed below 400 °C. However, when thinned to the atomic scale, small variations in defect density, interface roughness, or trap states can cause dramatic shifts in leakage current, threshold voltage, and mobility, creating a design bottleneck for back‑end‑of‑line integration.

The NTU team addressed this bottleneck by developing a unified analytical framework that simultaneously accounts for band transport, trap‑assisted conduction, interface disorder, and roughness‑induced scattering. Experimental validation across a thickness span of 2 nm to 13 nm showed that tungsten‑doped indium‑oxide (IWO) delivers lower off‑state leakage and a more stable gate‑dielectric interface compared with pure In2O3. By extracting trap density and energy‑distribution width directly from measured I‑V curves, the model links these microscopic parameters to macroscopic device metrics such as subthreshold slope and mobility degradation. The inclusion of a thickness‑dependent mobility term captures the increasing impact of surface roughness as electrons are forced closer to the gate in ultrathin channels.

For the semiconductor industry, the significance lies in turning empirical observations into a predictive design methodology. Engineers can now forecast how adjustments in channel thickness, doping level, or interface engineering will affect key performance targets, reducing the need for costly iterative prototyping. This capability accelerates the deployment of low‑leakage, normally‑off oxide transistors in heterogeneous 3D stacks, supporting higher functional density and lower power budgets. As 3D integration moves from research labs to volume production, such physics‑based design tools will be essential for maintaining yield, reliability, and competitive time‑to‑market.