EE Times – Designlines/AI & ML

EE Times – Designlines/AI & ML

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EE Times’ AI/ML and designlines frequently intersect with semiconductor hardware and EDA.

Gartner Says Supply Chain Confront Geopolitical and AI Challenges
NewsMay 29, 2026

Gartner Says Supply Chain Confront Geopolitical and AI Challenges

At Gartner’s Supply Chain Symposium, analyst Alejandro Santalo warned that supply‑chain leaders face a dual shock from tightening geopolitics and AI‑driven capacity constraints. He urged executives to build operational flexibility, diversify sourcing, and secure long‑term semiconductor allocations as hyperscalers reshape...

By EE Times – Designlines/AI & ML
Majestic Labs Raises $100M for Memory Pooling AI Server
NewsMay 28, 2026

Majestic Labs Raises $100M for Memory Pooling AI Server

Majestic Labs announced a $100 million Series A round to fund its memory‑pooled AI server, which promises up to 100 TB of DRAM per accelerator—equivalent to the capacity of ten GPU racks in a single box. The design separates memory from compute, using...

By EE Times – Designlines/AI & ML
Chiplets, Ecosystems, and Europe’s Post-Fab Semiconductor Strategy
NewsMay 28, 2026

Chiplets, Ecosystems, and Europe’s Post-Fab Semiconductor Strategy

Europe’s semiconductor share is projected to fall to about 6% in 2026, prompting policymakers to pivot from pure fab investment to a broader ecosystem strategy under Chips Act 2.0. The continent is betting on chiplets—modular building blocks linked by advanced packaging—to...

By EE Times – Designlines/AI & ML
Vicinity Unveils “TRAVE” — AI-Native SDR Platform at 5G-ACIA Frankfurt
NewsMay 28, 2026

Vicinity Unveils “TRAVE” — AI-Native SDR Platform at 5G-ACIA Frankfurt

Vicinity Technologies introduced TRAVE, an AI‑native 5G/6G software‑defined radio platform, at the 5G‑ACIA conference in Frankfurt. Built on NXP’s i.MX 95 processor and Layerscape chips, the system offers programmable PHY/MAC, native mesh, sidelink networking, and ultra‑low latency for industrial use cases....

By EE Times – Designlines/AI & ML
Intelligent, Configurable I/O: Edge Autonomy, Thermal Efficiency, and Higher Uptime in Industrial Control Systems
NewsMay 27, 2026

Intelligent, Configurable I/O: Edge Autonomy, Thermal Efficiency, and Higher Uptime in Industrial Control Systems

The paper examines how intelligent, configurable I/O is reshaping industrial control systems. By moving from fixed‑function to software‑defined channel assignment, a single I/O module can handle multiple signal types and adapt to late‑stage design changes. This flexibility reduces SKU count,...

By EE Times – Designlines/AI & ML
Startup Boosts Scale-Up to 1000+ GPUs in a Single Domain
NewsMay 27, 2026

Startup Boosts Scale-Up to 1000+ GPUs in a Single Domain

Delos Data unveiled its Nonstop AI platform, a disaggregated server design that can link more than 1,000 GPUs in a single scale‑up domain. By using nine OSFP ports per accelerator and 72 × 200 Gb/s connections per server, the system offers flexible topologies and...

By EE Times – Designlines/AI & ML
LightSpeed Photonics Targets AI Data Centers With 400-Gbps Near-Packaged Optical Interconnects
NewsMay 26, 2026

LightSpeed Photonics Targets AI Data Centers With 400-Gbps Near-Packaged Optical Interconnects

LightSpeed Photonics unveiled a 400‑Gbps solderable optical transceiver that is 20× smaller, consumes about 2 W, and offers up to four times lower latency than traditional pluggable modules. The PCB‑level “light engine” eliminates long copper traces and DSP retimers, promising 50‑75%...

By EE Times – Designlines/AI & ML
You May Not Know Actions Technology, But You’ve Definitely “Heard” It
NewsMay 25, 2026

You May Not Know Actions Technology, But You’ve Definitely “Heard” It

Actions Technology, a Zhuhai‑based IC designer, has evolved from pioneering China’s first MP3 SoC in 2001 to supplying high‑fidelity Bluetooth and proprietary 2.4 GHz audio chips for leading global consumer‑audio brands. Its self‑developed Bluetooth stack and NGPP‑2.4G protocol achieve 9 ms latency,...

By EE Times – Designlines/AI & ML
Realising the Benefits of Quality Inspection Reports
NewsMay 25, 2026

Realising the Benefits of Quality Inspection Reports

PCBWay has released 14 independent quality inspection reports generated by Centre Testing International, showcasing thermal, mechanical and electrical performance that exceeds typical industry benchmarks. The reports reveal a glass transition temperature of 169.6 °C, a coefficient of thermal expansion of 37.4 ppm/°C,...

By EE Times – Designlines/AI & ML
Imec Says AI Scaling Needs More Orchestration Across Research, Design, Manufacturing
NewsMay 22, 2026

Imec Says AI Scaling Needs More Orchestration Across Research, Design, Manufacturing

At ITF World 2026, imec CEO Patrick Vandenameele likened AI scaling to a violin that needs an orchestra, stressing that research, design, and manufacturing must operate in concert. He urged deeper collaboration among foundries, fabless firms, EDA vendors, equipment suppliers,...

By EE Times – Designlines/AI & ML
Gartner Urges Supply Chain Execs to Adopt Autonomous Business Strategies
NewsMay 21, 2026

Gartner Urges Supply Chain Execs to Adopt Autonomous Business Strategies

At Gartner’s Supply Chain Symposium, analyst Alan O’Keeffe urged chief supply‑chain officers to move beyond task‑level automation toward fully autonomous business operations. He highlighted that 80% of CEOs view current digital strategies as inadequate for an AI‑driven future, and that...

By EE Times – Designlines/AI & ML
Scaling the Next Generation of Multi-Die Systems
NewsMay 21, 2026

Scaling the Next Generation of Multi-Die Systems

The EE Times virtual conference on June 23‑24 will examine how to scale next‑generation multi‑die chiplet systems for AI workloads. Sessions focus on accelerating design flows, advanced packaging, interconnect standards and the thermal, power and yield challenges that arise at production...

By EE Times – Designlines/AI & ML
When Arm Meets RISC-V: SiPearl, Semidynamics to Co-Develop Sovereign AI Platform
NewsMay 20, 2026

When Arm Meets RISC-V: SiPearl, Semidynamics to Co-Develop Sovereign AI Platform

SiPearl and Semidynamics announced a joint effort to build Europe’s first sovereign rack‑scale AI platform, pairing SiPearl’s Arm‑based Rhea2 CPUs with Semidynamics’ RISC‑V inference accelerators. The first‑generation system will rely on DDR memory for the CPUs and full CPU‑accelerator memory...

By EE Times – Designlines/AI & ML
Imec’s Patrick Vandenameele: Full-Stack Innovation Is the Name of the Game
NewsMay 19, 2026

Imec’s Patrick Vandenameele: Full-Stack Innovation Is the Name of the Game

Imec CEO Patrick Vandenameele said full‑stack, cross‑technology co‑optimization will drive semiconductor innovation over the next decade. He highlighted five shifts: angstrom‑scale system co‑optimization, silicon photonics, strategic memory, chiplet‑based edge computing, and industrial quantum computing. Imec is expanding its role with...

By EE Times – Designlines/AI & ML
EE Times – Designlines/AI & ML | Pulse