Designing Better 2D Electronics: Addressing Anisotropic Conductivity to Cut Contact Resistance

Why It Matters

Accurate contact resistance modeling is critical for scaling 2D semiconductor devices in smartphones, AI chips, and EV batteries, directly impacting performance and reliability. The new model gives designers a physics‑based tool to minimize resistance without costly trial‑and‑error.

Key Takeaways

• New model captures anisotropic conductivity in 2D contacts.
• Eliminates fitting parameters for spreading resistance.
• Shows out-of-plane conductivity key to lower resistance.
• Guides design of planar and disc contacts.

Pulse Analysis

The push toward atomically thin semiconductors has turned 2D materials such as molybdenum disulfide, graphene, and high‑oriented pyrolytic graphite into cornerstones of next‑generation electronics. Their layered crystal structure, however, introduces a pronounced anisotropy: electrons travel readily within the basal plane but encounter weak van der Waals coupling between layers. This disparity creates current crowding at vertical contacts, where charge carriers pile up near the edge of a metal pad, generating high spreading resistance that can overheat the device and degrade speed. Conventional models, which assume isotropic transport, fail to capture these effects, leading designers to rely on empirical fitting that obscures the underlying physics.

The University of Michigan team answered this gap with an exact field solution derived from second‑order Laplace equations that incorporates both anisotropic conductivity tensors and the actual dimensions of the contact and film. By solving the differential equations analytically, the model predicts the voltage and current distribution without resorting to adjustable parameters. Finite‑element simulations confirmed the analytical results, and experimental measurements on MoS₂ thin films and pyrolytic graphite matched the predicted spreading resistance across a range of contact sizes and shapes. The approach works equally for planar and disc‑shaped contacts, demonstrating that geometry matters less than the material’s out‑of‑plane conductivity.

For chip manufacturers, the practical upshot is clear: improving the vertical conductivity of the 2D stack—through doping, interlayer engineering, or novel contact metals—offers the most direct route to lower contact resistance. Designers can now size contacts and select film thicknesses with confidence, using the model to avoid costly prototyping cycles. As AI accelerators, flexible displays, and electric‑vehicle power modules increasingly adopt 2D channels, the ability to predict and mitigate current crowding will translate into higher efficiency, longer device lifetimes, and faster time‑to‑market. The framework also opens a pathway for academic researchers to extract intrinsic transport parameters from measurement data, accelerating material discovery.