Hardware Videos

Digital Design & Computer Architecture D3: Problem-Solving Session 3 (Spring 2026)

The session introduced Verilog as a hardware description language, emphasizing that it models physical circuits rather than behaving like a traditional software language such as Java. The instructor walked through the creation of an "odd counter"—a finite‑state machine that counts 1, 3, 5, 7, 9, 11 and then wraps—to illustrate core Verilog concepts, including module declarations, inputs, outputs, and register definitions. Key design principles were highlighted: hierarchical design enables reuse of lower‑level primitives (e.g., two‑bit adders) within larger modules; always blocks with appropriate sensitivity lists drive state transitions; and the distinction between blocking and non‑blocking assignments determines simulation versus synthesis behavior. The lecture also covered common pitfalls, such as treating registers as ordinary variables and assigning to non‑registers inside always blocks, which trigger clear compiler errors. During the coding demo, the instructor demonstrated a syntax error when attempting a procedural assignment to a non‑register, then corrected it by declaring the signal as a reg. A discussion on reset handling showed how to add an asynchronous reset input to guarantee a known initial state. The session also clarified why consolidating output assignments into a single always block avoids ambiguous behavior when clock and reset events coincide. For students, mastering these Verilog fundamentals is essential for building reliable digital designs, debugging efficiently, and meeting industry expectations for synthesizable hardware code. Proper hierarchical structuring, disciplined use of always blocks, and clear reset logic translate directly into reduced development time and higher-quality ASIC or FPGA projects.