Hardware Social Media and Updates

AVX‑512’s Extra Registers Eliminate FMA Spill Bottleneck

For a balanced architecture, it feels like there should be a rule of the form: 3*[fma latency]*[fma unit count] < [register name count] The 3 comes from the fact that you have up to 3 operands that feed each FMA. For example: on x64, the left side often looks like 3*4*2 = 24. Thus, on SSE and AVX1/2, it's hard to avoid spills (or underutilization, your choice) because 24 is greater than the register name count of 16. If you try to interleave serial computations the way you would want (which is to have 8 independent FMAs available at all times to cover the 4-cycle latency for both units), you will run out of register names, since even just providing 2 persistent operands for an FMA requires all 16 register names right there. On AVX-512, by contrast, you have 32 registers, so it flips to 24 < 32, and now interleaving 8 chains becomes relatively straightforward. X is probably not the best place to try to explain this, but, I feel like people who work with these sorts of things will know what I'm talking about :) Has anyone else noticed this pattern, or am I overgeneralizing?