Technology Videos

AHB Interview Questions and Answers | Part 1 | AMBA AHB Protocol Interview Prep

The video is an interview-prep lesson on the AMBA AHB protocol covering three topics: how pipeline timing and inserted wait states affect the HADDR/HTRANS signals during an INCR4 transfer, the difference between single, INCR (undefined length) and fixed-length bursts (INCR4/INCR16) and when to use each, and the mandatory two-cycle error response where the slave asserts HRESP=01 with HREADYOUT=0 then releases HREADYOUT=1 in the next cycle. The instructor explains that address phases are pipelined—addresses for beat N+1 appear during beat N’s data phase—and that when HREADYOUT=0 the address/control signals must be held stable. For burst types, undefined INCR is used when transfer count is data-dependent (e.g., scatter-gather) while fixed-length bursts let slaves prefetch and optimize throughput. On error, the slave must stall one cycle to signal the error and the master must abort remaining burst transfers upon receiving HRESP=01.