Nanotech News and Headlines

Practical Design Guidelines for Atom-Thin Oxide Transistors Enable Reliable 3D Chip Integration

Researchers at National Taiwan University introduced a unified analytical framework that captures how channel thickness, trap states, interface quality, and surface roughness jointly dictate the performance of atom‑thin indium‑oxide and tungsten‑doped indium‑oxide transistors. The model accurately reproduces I‑V characteristics for devices ranging from 2 nm to 13 nm, revealing that tungsten doping suppresses leakage and stabilizes the gate‑dielectric interface. By translating experimental data into predictive design rules, the work offers a practical pathway to fabricate low‑leakage, normally‑off oxide transistors compatible with back‑end‑of‑line temperatures below 400 °C. This enables reliable three‑dimensional chip stacking without compromising underlying layers.