
Intel's Nova Lake desktop line rumored to jump to 44 cores
A leaked configuration shows Intel's upcoming Nova Lake‑S desktop processors moving from a 42‑core to a 44‑core SKU. The new design pairs two identical 8‑performance‑core plus 12‑efficient‑core compute tiles, freeing up a 6P+12E tile that could be sold as lower‑priced, locked variants while retaining on‑die big last‑level cache.

KAIST researchers have unveiled a "smart gate" semiconductor structure that uses a novel boron oxynitride (BON) tunneling layer to overcome scaling limits in 3D V‑NAND flash memory. The asymmetric energy‑barrier design accelerates erase operations by up to 23‑fold while maintaining data integrity, even under the demanding penta‑level cell (PLC) regime. Experimental chips showed three‑times better voltage‑distribution control and sustained performance after tens of thousands of program‑erase cycles. The breakthrough was presented at the IEEE International Electron Devices Meeting and earned the Grand Prize at Samsung’s Human Tech Paper Awards.

Jmem Tek has joined GlobalFoundries’ GlobalSolutions™ Ecosystem as an official IP Network Partner, bringing its proprietary Physical Unclonable Function (PUF) and post‑quantum cryptography (PQC) IP to GlobalFoundries customers worldwide. The partnership gives semiconductor designers access to silicon‑proven hardware root‑of‑trust, secure...
CEA‑Leti and Fraunhofer IPMS have completed the first exchange of ferroelectric memory wafers within the EU‑funded FAMES Pilot Line, proving a shared platform for advanced embedded non‑volatile memory development. The exchange used 300 mm CMOS cleanrooms to process hafnium‑zirconium oxide (HZO)...