Know What's Happening in Semiconductors
Know What's Happening in Semiconductors
Intel's Nova Lake desktop line rumored to jump to 44 cores
A leaked configuration shows Intel's upcoming Nova Lake‑S desktop processors moving from a 42‑core to a 44‑core SKU. The new design pairs two identical 8‑performance‑core plus 12‑efficient‑core compute tiles, freeing up a 6P+12E tile that could be sold as lower‑priced, locked variants while retaining on‑die big last‑level cache.
Fujitsu and Rapidus announced a joint development of a 1.4 nm neural processing unit (NPU) aimed at AI inference in servers. The project, costing roughly 58 billion yen, will leverage Rapidus’s advanced node roadmap and Fujitsu’s Arm‑based Monaka CPU built on a 2 nm process, packaging both in a single package. Government subsidies are expected to cover a large portion of the expense, reflecting Japan’s push for a domestic semiconductor supply chain. The collaboration also positions Rapidus toward its 1.4 nm target around 2029 while Fujitsu continues to rely on Nvidia and AMD GPUs for training workloads.
Mekotronics introduced the R57-5S, a Rockchip RK3576‑based mini PC with an integrated 5‑inch inclined touchscreen aimed at kiosk and digital‑signage markets. The device offers up to 16 GB LPDDR5 RAM, up to 1 TB UFS storage, dual GbE, Wi‑Fi 5, Bluetooth 5.1, optional 4G...
onsemi announced that its next‑generation hybrid power integrated modules (PIMs) will be used in Sineng Electric’s 430 kW liquid‑cooled string energy storage system and 320 kW utility‑scale solar inverter. The FS7 IGBT and EliteSiC‑based F5BP modules deliver 32% higher power density and...
The article outlines a security framework for chiplet‑based systems, emphasizing that each chiplet must possess a verifiable identity tied to a platform‑wide trust chain. It describes two provisioning patterns—certificate‑based external provisioning and silicon‑derived (PUF) self‑generated keys—and explains how both feed...
Design teams moving to 3D‑IC architectures face intertwined power, thermal and mechanical challenges that can jeopardize yield and reliability. Traditional 2D verification tools fall short because stacked dies introduce new materials and complex inter‑dependencies. Siemens EDA’s Calibre 3DStress combined with...
The surge in AI infrastructure is creating a memory supercycle that pushes leading chipmakers to prioritize high‑margin products such as HBM, DDR5 and advanced NAND. DRAM prices are projected to jump roughly 90% quarter‑over‑quarter, while NAND could rise about 60%,...
Synopsys became the first company to earn ISO/PAS 8800 certification for its MACsec IP, a standard that secures Ethernet communication inside vehicles. The certification, validated by SGS TÜV Saar, confirms that the IP not only protects data integrity but also meets the...
The article examines how modern power electronics—especially multi‑level converters, silicon‑carbide (SiC) devices, and advanced power‑management ICs—are improving efficiency in electric vehicle (EV) and robot battery systems. It highlights fast‑charging challenges, noting that 15‑minute 0‑80% charges and 750 kW superchargers generate heat...
Bit flipping, once a rare reliability glitch, has become a systemic risk as semiconductor nodes shrink, clock speeds rise, and operating voltages drop, exposing aerospace, automotive and data‑center chips to silent data corruption. The phenomenon is driven by cosmic radiation,...
At Embedded World 2026, Synaptics demonstrated that artificial intelligence is moving off the cloud and onto the device, delivering real‑time, context‑aware capabilities at the edge. The company showcased the SYN765x platform, which bundles Wi‑Fi 7, Bluetooth 6.0 and on‑chip AI compute for...
Intel unveiled two core configurations for its upcoming Core Ultra 400HX “Nova Lake‑HX” mobile processor, targeting high‑end gaming laptops and portable workstations. The flagship SKU packs 8 performance‑core Coyote Cove P‑cores, 16 Arctic Wolf efficiency cores and 4 low‑power island...
Altera Corp. is deepening its two‑decade partnership with Arm by integrating its data‑center‑grade FPGAs with Arm’s new AGI CPU built on the Neoverse CSS V3 architecture. The combined solution targets AI‑focused data centers, promising low‑latency, highly flexible and scalable compute...
Molex announced the completion of its acquisition of Smiths Interconnect, the UK‑based subsidiary of Smiths Group, marking the largest deal in Molex’s history. The purchase adds a portfolio of ruggedized connectors, RF components, optical transceivers and semiconductor‑test expertise, extending Molex’s...
SEMI projects worldwide 300mm fab equipment spending to rise 18% to $133 billion in 2026 and surpass $150 billion in 2027, reaching $172 billion by 2029. The surge is driven by exploding AI chip demand for data‑center and edge workloads and by regional...
Taiwan is shifting its wide‑bandgap (WBG) strategy from pure device innovation to integrated packaging, testing, and system deployment. NIKO‑SEM, a fabless power‑semiconductor designer, has broadened its portfolio from silicon MOSFETs to silicon‑carbide (SiC) and gallium‑nitride (GaN) power modules. The island...
Elon Musk unveiled a joint Tesla‑SpaceX semiconductor fab, dubbed Terafab, slated for Austin, Texas with an estimated $20‑$25 billion investment. The plant would integrate logic, memory, and radiation‑hard chip production, targeting a 2nm process and on‑site packaging. No concrete timeline was...
Infineon unveiled the TDM24745T quad‑phase power module, featuring a trans‑inductor voltage regulator (TLVR) architecture that delivers up to 320 A peak current in a 9×10×5 mm footprint. The module integrates four power stages, proprietary magnetics, and decoupling capacitors, achieving a current density...
Diodes has introduced the DMTH10H1M7SPGWQ, a 100‑V MOSFET that joins its existing 40‑80 V lineup for automotive applications. The device offers a low 1.5 mΩ on‑resistance, making it ideal for 48‑V BLDC motor drives in power‑steering and braking systems. Packaged in a...
Texas Instruments introduced two isolated DC/DC modules—UCC34141-Q1 and UCC33420—built on its IsoShield multichip packaging. The architecture co‑packs a planar transformer with the power stage, delivering up to three times the power density of traditional discrete solutions and shrinking board area...
Tower Semiconductor announced it will acquire full ownership of its 300mm Fab 7 in Uozu, Japan, while Nuvoton will take complete control of the 200mm Fab 5. The restructuring includes long‑term supply agreements to avoid any disruption for existing customers...
Intel’s latest MLPerf Inference v6.0 results highlight its Xeon 6 CPUs paired with Arc Pro B70/B65 GPUs delivering open, scalable AI performance across workstations, data‑center, and edge workloads. A four‑GPU B70 configuration offers 128 GB of VRAM and can run 120‑billion‑parameter models, achieving...
The World Trade Organization failed to extend the two‑year “Moratorium on Customs Duties on Electronic Transmissions” at its Yaoundé ministerial, allowing the measure to lapse. The moratorium has shielded digital goods, software services and semiconductor‑related data flows from tariffs for...
SEMI projects global 300mm fab equipment spending to rise 18% to $133 billion in 2026 and 14% to $151 billion in 2027. The surge is fueled by exploding AI chip demand for data centers and edge devices and by regional pushes for...
Intel announced a definitive agreement to repurchase Apollo’s 49% equity stake in the Fab 34 joint venture for $14.2 billion. The buy‑back will be financed with cash on hand and roughly $6.5 billion of new debt, aiming to restore full ownership of the...
AMD announced that its Instinct MI355X GPUs have broken the 1 million‑tokens‑per‑second barrier in the MLPerf Inference 6.0 benchmark, delivering up to 3.1× higher throughput than the prior MI325X. The GPUs, built on the 3 nm CDNA 4 architecture with FP4/FP6 support and up...
Good discussion here on copper/optical with @mediatek. They are pushing the limits with NPC (near package copper) and CPC (co-packaged copper) at 400G per lane, with distinct efficiencies in those solutions. But past that, most likely optical NPO/CPO.
Being flexible, customer friendly, and willing to work with as little or as much customer owned IP the customer wants is an approach @mediatek does seem well positioned for. If you believe customer owned tooling becomes a thing. They seem competitive....
Alchip Technologies announced a dedicated 2nm ASIC design platform and completed a successful 2nm test‑chip tape‑out featuring its AP‑Link‑3D interface. The platform supports 2.5D and 3D chiplet integration, enabling high‑performance, power‑efficient silicon for AI and high‑performance computing workloads. By adopting...
This may be the money slide for @mediatek on custom XPU solutions. One area I do believe they have a distinct advantage is their privileged relationship with TSMC. https://t.co/2dIFSrVRMz
The XPU is one part of what is now becoming a custom solutions approach (not just the compute ASIC) but @mediatek showing what they have been investing in across the custom solution stack. Hadn’t seen many of these details before....
EPC Space announced two new half‑bridge buck evaluation boards, the EPC7C010 (100 V/20 A) and EPC7C011 (200 V/10 A), built around radiation‑hardened eGaN HEMTs and isolated gate drivers. Both platforms are optimized for 350 kHz operation but can run from 50 kHz to 1.5 MHz, delivering peak...
In a supply chain world of constraints having a diverse supply chain and key partners gives customers higher confidence in execution. @mediatek showing that depth as an advantage for their datacenter efforts. https://t.co/OMAXc4kkPE
Getting into the guts of @MediaTek data center/custom XPU details but this slide is informative of market work they have been doing in this space since 2011. Expecting more details on SerDes, advanced packaging, fabric, and their networking capabilities. https://t.co/OWT2MbypXK
AI workloads are pushing XPU power consumption from roughly 1‑1.5 kW today to over 5 kW by 2030. To handle the surge, hyperscale data centers are replacing traditional AC‑DC‑AC distribution with high‑voltage direct current (HVDC) architectures, using ±400 V or 800 V DC links....
SEC Co. has completed development of the Semi‑Scan‑SW, an automated inline X‑ray inspection system for high‑bandwidth memory (HBM) production. The tool detects internal defects as small as 3‑5 µm across HBM stacking, through‑glass‑via (TGV) and wafer‑level packaging (WLP) processes. SEC will...
Came across some interesting things from supply chain friendlies on memory. And... Not going to get better anytime soon. Next year will be worse than this year.
SEMI’s latest 300 mm Fab Outlook projects worldwide fab equipment spending to jump 18% to $133 billion in 2026 and 14% to $151 billion in 2027, marking the first time the market exceeds $150 billion. The surge is driven by exploding AI chip demand...
The article revisits the classic memory‑hog cycle—where surging demand fuels price spikes, capacity expands, and oversupply triggers crashes—through the lens of today’s AI boom. It highlights that AI accelerators now consume roughly 70% of high‑end DRAM, pushing memory prices up...
Intel announced it will repurchase the 49% equity interest in the Fab 34 joint venture in Ireland from Apollo for $14.2 billion. The stake was originally sold to Apollo‑managed funds in 2024 for $11.2 billion, giving Intel equity‑like capital while preserving balance‑sheet strength....
Semiconductor Intelligence projects total industry capital spending to reach $200 billion in 2026, a 20% rise from 2025 and outpacing market growth. TSMC remains the largest spender, targeting $52‑$56 billion, while most other foundries stay flat except GlobalFoundries’ 70% increase. Elon Musk’s...
NVIDIA announced a $2 billion investment in Marvell Technology and an expanded NVLink Fusion partnership. The deal links Marvell’s silicon to NVIDIA’s AI factory and AI‑RAN ecosystem, giving customers broader options for next‑generation infrastructure. Both companies will also co‑develop silicon‑photonic solutions....
Silvaco Group announced an expanded strategic partnership with Taiwan's Advanced Power Electronics Corp (APEC) to deepen the use of its Victory Device, Gateway, and SmartSpice simulation tools. The collaboration gives APEC broader access to Silvaco's TCAD and EDA solutions, aiming...
Raspberry Pi announced another price increase after a seven‑fold rise in LPDDR4 DRAM costs, affecting all 4 GB and larger models of the Pi 4 and Pi 5. Prices for these SKUs will climb between $25 and $100, pushing the 16 GB Pi 5 to...
Apple announced a $400 million investment with U.S. suppliers Bosch, Cirrus Logic, TDK and Qnity Electronics to broaden domestic chip production, extending its broader $600 billion manufacturing plan. TDK will start U.S. sensor component fabrication for smartphone cameras, while Bosch will produce...
Japanese memory maker Kioxia announced it will discontinue a range of older NAND flash products built on 32 nm, 24 nm and 15 nm process nodes, including floating‑gate and BiCS FLASH gen.3 devices. The phase‑out covers SLC, MLC and TLC variants in wafer, BGA, TSOP,...
ASUS unveiled the UGen300 USB AI Accelerator, its first AI‑focused USB device powered by Hailo’s 10H processor delivering 40 AI TOPS. The compact 105 × 50 × 18 mm module packs 8 GB of LPDDR4 memory and draws only 2.5 W via a USB‑C interface. It offers plug‑and‑play compatibility...
AI compute demand propelled the top ten global fabless IC designers to $359.4 billion in 2025, a 44 % year‑over‑year increase. NVIDIA led the pack with $205.7 billion revenue, accounting for 57 % of the group’s total, while Broadcom rose to second place thanks...
Semiconductor test equipment maker Aehr Test Systems announced an initial order from a major, unnamed networking supplier developing silicon‑photonic transceivers for hyperscale AI and cloud data centers. The order includes several FOX‑XP wafer‑level burn‑in systems capable of testing nine wafers...
Side‑channel leakage often surfaces only after first silicon, forcing expensive redesigns. The Inspector Pre‑Silicon framework embeds side‑channel analysis into RTL and gate‑level verification, generating test vectors and statistical metrics to identify leakage early. By providing actionable, module‑level insights throughout the...
The article reviews the historical scaling limits of DDR DRAM and highlights that DDR5 now supports only one DIMM per channel, a trend that may continue with DDR6. Industry insiders speculate that DDR7 could eliminate DIMMs entirely, dramatically reducing bus...
